src/peripherals/mux/mux.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 package mux;
  15         /*==== Package imports ==== */
  16         import TriState          ::*;
  17         import Vector                            ::*;
  18         import BUtils::*;
  19         import ConfigReg                        ::*;
  20         /*============================ */
  21         /*===== Project Imports ===== */
  22         import Semi_FIFOF        :: *;
  23         import AXI4_Lite_Types   :: *;
  24         /*============================ */
  25     `include "instance_defines.bsv"
  26
  27     interface MUX_config#(numeric type ionum);
  28                 (*always_ready,always_enabled*)
  29                 method Vector#(ionum,Bit#(2))   mux;
  30     endinterface
  31
  32         interface MUX#(numeric type ionum);
  33         interface MUX_config#(ionum) mux_config;
  34             interface AXI4_Lite_Slave_IFC#(`PADDR,`DATA,`USERSPACE) axi_slave;
  35         endinterface
  36
  37 //      (*synthesize*)
  38         module mkmux#(Bit#(TMul#(ionum_, 2)) defvalue)(MUX#(ionum_));
  39     let ionum=valueOf(ionum_);
  40           Vector#(ionum_,ConfigReg#(Bit#(2))) muxer_reg ;
  41     for(Integer i=0;i<ionum;i=i+ 1)
  42       muxer_reg[i]<-mkConfigReg(defvalue[i*2+ 1:i*2]);
  43
  44                 AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `DATA, `USERSPACE)  s_xactor <- mkAXI4_Lite_Slave_Xactor;
  45                 rule rl_wr_respond;
  46                         // Get the wr request
  47             //aw is write address, w is write data
  48       let aw <- pop_o (s_xactor.o_wr_addr);
  49       let w  <- pop_o (s_xactor.o_wr_data);
  50                 let b = AXI4_Lite_Wr_Resp {bresp: AXI4_LITE_OKAY, buser: aw.awuser};
  51                   if(aw.awaddr[5:0]=='h0)
  52                     for(Integer i=0;i<min(ionum, 16);i=i+1) begin
  53           muxer_reg[i]<= w.wdata[i*2+1:i*2];
  54                         end
  55                   else if(aw.awaddr[5:0]=='h4 && ionum>=16)
  56                         for(Integer i=0;i<ionum-16;i=i+1) begin
  57           muxer_reg[i+16]<= w.wdata[i*2+1:i*2];
  58                         end
  59                         else
  60                                 b.bresp=AXI4_LITE_SLVERR;
  61         s_xactor.i_wr_resp.enq (b);
  62                 endrule
  63
  64                 rule rl_rd_respond;
  65             // Get the read request
  66             //ar is read address, r is read data
  67                         let ar<- pop_o(s_xactor.o_rd_addr);
  68                         Bit#(32) temp=0;
  69                         AXI4_Lite_Rd_Data#(`DATA,`USERSPACE) r = AXI4_Lite_Rd_Data {rresp: AXI4_LITE_OKAY, rdata: ?, ruser: 0};
  70                   if(ar.araddr[5:0]=='h0)begin
  71                         for(Integer i=0;i<min(ionum, 16);i=i+1) begin
  72           temp[i*2+ 1:i*2]=muxer_reg[i];
  73                         end
  74         r.rdata=duplicate(temp);
  75       end
  76                   else if(ar.araddr[5:0]=='h4 && ionum>=16)begin
  77                         for(Integer i=0;i<ionum-16;i=i+1) begin
  78           temp[i*2+ 1:i*2]=muxer_reg[i+ 16];
  79                         end
  80         r.rdata=duplicate(temp);
  81       end
  82                         else
  83                                 r.rresp=AXI4_LITE_SLVERR;
  84                         s_xactor.i_rd_data.enq(r);
  85                 endrule
  86
  87                 interface axi_slave= s_xactor.axi_side;
  88     interface mux_config=interface MUX_config
  89                 method Vector#(ionum,Bit#(2))   mux;
  90                         Vector#(ionum,Bit#(2)) temp;
  91                         for(Integer i=0;i<ionum;i=i+1)
  92                                 temp[i]=pack(muxer_reg[i]);
  93                         return temp;
  94                 endmethod
  95     endinterface;
  96         endmodule
  97
  98 endpackage
  99