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add first peripheral set
[shakti-peripherals.git] / src / peripherals / qspi / qspi.bsv
1 /*
2 Copyright (c) 2013, IIT Madras
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
6
7 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
8 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
9 * Neither the name of IIT Madras nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
10
11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
13 */
14 package qspi;
15 /*
16 TODOs
17 To use the following registers:
18 dcr_csht
19 * Done Pre-scaler.
20 > Memory mapped mode should continue to fetch data and fill the fifo even if the Core
21 is not requesting
22 * Done Status polling mode.
23 > This could not be replicated since the tof flag is set.
24 Memory mapped mode with dcyc =10 creates an extra cycle after Dummy phase.
25 > Data Read phase is on posedge and Data write is on negdege
26 -- send the received arid and bid's so that DMA can identify. duplicate instead of extend
27 */
28 import TriState::*;
29 import ConcatReg ::*;
30 import Semi_FIFOF :: *;
31 import AXI4_Lite_Types :: *;
32 import AXI4_Lite_Fabric :: *;
33 import FIFO::*;
34 import FIFOF::*;
35 import SpecialFIFOs::*;
36 import MIMO::*;
37 import DefaultValue :: *;
38 `include "instance_defines.bsv"
39 `include "qspi.defs"
40 import ConfigReg::*;
41 import Vector::*;
42 import UniqueWrappers :: * ;
43 import DReg::*;
44 import BUtils::*;
45 (*always_ready, always_enabled*)
46 interface QSPI_out;
47 /*(* always_ready, result="clk_o" *) */ method bit clk_o;
48 /*(* always_ready, result="io_o" *) */ method Bit#(4) io_o;
49 /*(* always_ready, result="io0_sdio_ctrl" *) */ method Bit#(9) io0_sdio_ctrl;
50 /*(* always_ready, result="io1_sdio_ctrl" *) */ method Bit#(9) io1_sdio_ctrl;
51 /*(* always_ready, result="io2_sdio_ctrl" *) */ method Bit#(9) io2_sdio_ctrl;
52 /*(* always_ready, result="io3_sdio_ctrl" *) */ method Bit#(9) io3_sdio_ctrl;
53 /*(* always_ready, result="io_enable" *)*/ method Bit#(4) io_enable;
54 /*(* always_ready, always_enabled *) */ method Action io_i ((* port="io_i" *) Bit#(4) io_in); // in
55 /*(* always_ready, result="ncs_o" *) */ method bit ncs_o;
56 endinterface
57
58 interface Ifc_qspi;
59 interface QSPI_out out;
60 interface AXI4_Lite_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) slave;
61 method Bit#(6) interrupts; // 0=TOF, 1=SMF, 2=Threshold, 3=TCF, 4=TEF 5 = request_ready
62 `ifdef simulate
63 method Phase curphase;
64 `endif
65 endinterface
66
67 function Reg#(t) readOnlyReg(t r);
68 return (interface Reg;
69 method t _read = r;
70 method Action _write(t x) = noAction;
71 endinterface);
72 endfunction
73
74 function Reg#(t) conditionalWrite(Reg#(t) r, Bool a);
75 return (interface Reg;
76 method t _read = r._read;
77 method Action _write(t x);
78 if(a)
79 r._write(x);
80 endmethod
81 endinterface);
82 endfunction
83
84 function Reg#(t) clearSideEffect(Reg#(t) r, Action a, Action b)
85 provisos( Literal#(t),Eq#(t));
86 return (interface Reg;
87 method t _read = r._read;
88 method Action _write(t x);
89 r._write(x);
90 if(x==1) begin
91 a;
92 b;
93 end
94 endmethod
95 endinterface);
96 endfunction
97
98 function Reg#(Bit#(32)) writeSideEffect(Reg#(Bit#(32)) r, Action a);
99 return (interface Reg;
100 method Bit#(32) _read = r._read;
101 method Action _write(Bit#(32) x);
102 r._write(x);
103 a;
104 endmethod
105 endinterface);
106 endfunction
107
108 function Reg#(Bit#(n)) writeCCREffect(Reg#(Bit#(n)) r, Action a, Action b);
109 return (interface Reg;
110 method Bit#(n) _read = r._read;
111 method Action _write(Bit#(n) x);
112 r._write(x);
113 `ifdef verbose1 $display("x: %h",x); `endif
114 if(x[11:10]==0 && (x[27:26] == 'b00 || x[27:26]=='b01 || x[25:24]=='b0) && x[9:8]!=0) begin // no address required and nodata from firmware (i.e. no write)
115 a;
116 end
117 if(x[27:26]=='b11) //Memory Mapped Mode
118 b;
119 endmethod
120 endinterface);
121 endfunction
122
123 typedef enum {Instruction_phase=0,
124 Address_phase=1,
125 AlternateByte_phase=2,
126 Dummy_phase=3,
127 DataRead_phase=4,
128 DataWrite_phase=5,
129 Idle=6} Phase deriving (Bits,Eq,FShow);
130
131 (*synthesize*)
132 module mkqspi(Ifc_qspi);
133
134 AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE) s_xactor <- mkAXI4_Lite_Slave_Xactor;
135 /*************** List of implementation defined Registers *****************/
136 Reg#(bit) rg_clk <-mkReg(1);
137 Reg#(Bit#(8)) rg_clk_counter<-mkReg(0);
138 MIMOConfiguration cfg=defaultValue;
139 cfg.unguarded=True;
140 MIMO#(4,4,16,Bit#(8)) fifo <-mkMIMO(cfg);
141 Reg#(Phase) rg_phase <-mkReg(Idle);
142 Reg#(Phase) rg_phase_delayed <-mkReg(Idle);
143 Reg#(Bit#(4)) rg_output <-mkReg(0);
144 Reg#(Bit#(4)) rg_output_en <-mkReg(0);
145 Reg#(Bool) rg_input_en <-mkReg(False);
146 Wire#(Bit#(4)) rg_input <-mkDWire(0);
147 Reg#(Bit#(32)) rg_count_bits <-mkReg(0); // count bits to be transfered
148 Reg#(Bit#(32)) rg_count_bytes <-mkReg(0); // count bytes to be transfered
149 Wire#(Bool) wr_sdr_clock <-mkDWire(False); // use this to trigger posedge of sclk
150 Reg#(Bool) wr_sdr_delayed <- mkReg(False);
151 Reg#(Bool) wr_instruction_written<-mkDReg(False); // this wire is se when the instruction is written by the AXI Master
152 Reg#(Bool) wr_address_written<-mkDReg(False); // this wire is set when the address is written by the AXI Master
153 Reg#(Bool) wr_read_request_from_AXI<-mkDReg(False); // this wire is set when the address is written by the AXI Master
154 Reg#(Bool) wr_data_written<-mkDReg(False); // this wire is set when the data is written by the AXI Master
155 Reg#(Bool) instruction_sent<-mkReg(False); // This register is set when the instruction has been sent once to the flash
156 Reg#(Bit#(1)) ncs <-mkReg(1); // this is the chip select
157 Reg#(Bit#(1)) delay_ncs <-mkReg(1); // this is the chip select
158 Wire#(Bool) wr_status_read<-mkDWire(False); // this wire is set when the status register is written
159 Wire#(Bool) wr_data_read<-mkDWire(False); // this wire is set when the data register is written
160 Reg#(Bool) half_cycle_delay<-mkReg(False);
161 Reg#(Bit#(16)) timecounter<-mkReg(0);
162 Reg#(Bool) read_true <- mkReg(False);
163 Reg#(Bool) first_read <- mkReg(False);
164 /*************** End of implementation defined Registers *****************/
165
166 /*************** List of QSPI defined Registers *****************/
167 Reg#(Bit#(1)) sr_busy <-mkConfigReg(0); // set when the operation is in progress.
168 Reg#(Bit#(5)) sr_flevel <-mkReg(0); // FIFO Level. Number of valid bytes held in the FIFO. 0: empty
169 Reg#(Bit#(1)) sr_tof <-mkReg(0); // set when the timeout occurs.
170 Reg#(Bit#(1)) sr_smf <-mkReg(0); // set when the unmasked receieved data matches psmar.
171 Reg#(Bit#(1)) sr_ftf <-mkReg(0); // set when the FIFO threshold is reached.
172 Reg#(Bit#(1)) sr_tcf <-mkReg(0); // set when programmed number of data has been transfered or when aborted.
173 Reg#(Bit#(1)) delay_sr_tcf <-mkReg(0); // set when programmed number of data has been transfered or when aborted.
174 Reg#(Bit#(1)) sr_tef <-mkReg(0); // set when an error occurs on transfer.
175 Reg#(Bit#(32)) sr = concatReg9(readOnlyReg(19'd0),readOnlyReg(sr_flevel),readOnlyReg(2'd0),readOnlyReg(sr_busy),readOnlyReg(sr_tof),readOnlyReg(sr_smf),readOnlyReg(sr_ftf),readOnlyReg(sr_tcf),readOnlyReg(sr_tef));
176
177
178 Reg#(Bit#(8)) prescaler<-mkReg(0);
179 Reg#(Bit#(8)) cr_prescaler=conditionalWrite(prescaler,sr_busy==0); // prescaler register part of the control register.
180 Reg#(Bit#(1)) pmm <-mkReg(0);
181 Reg#(Bit#(1)) cr_pmm =conditionalWrite(pmm,sr_busy==0); // polling match mode. 0: AND match and 1: OR match.
182 Reg#(Bit#(1)) apms <-mkReg(0);
183 Reg#(Bit#(1)) cr_apms =conditionalWrite(apms,sr_busy==0); // automatic poll mode stop. 1: stop when match. 0: stopped by disabling qspi.
184 Reg#(Bit#(1)) cr_toie <-mkReg(0); // enabled interrupt on time-out.
185 Reg#(Bit#(1)) cr_smie <-mkReg(0); // enables status match interrupt.
186 Reg#(Bit#(1)) cr_ftie <-mkReg(0); // enables interrupt on FIFO threshold.
187 Reg#(Bit#(1)) cr_tcie <-mkReg(0); // enables interrupt on completion of transfer.
188 Reg#(Bit#(1)) cr_teie <-mkReg(0); // enables interrupt on error of transfer.
189 Reg#(Bit#(4)) cr_fthres<-mkReg(0); // defines the number of bytes in the FIFO that will cause the FTF in sr to be raised.
190 Reg#(Bit#(1)) fsel<-mkReg(0);
191 Reg#(Bit#(1)) cr_fsel=conditionalWrite(fsel,sr_busy==0); // used for flash memory selection TODO: Not required.
192 Reg#(Bit#(1)) dfm<-mkReg(0);
193 Reg#(Bit#(1)) cr_dfm =conditionalWrite(dfm,sr_busy==0); // used for dual flash mode TODO: Not required.
194 Reg#(Bit#(1)) sshift<-mkReg(0);
195 Reg#(Bit#(1)) cr_sshift =conditionalWrite(sshift,sr_busy==0); // sample shift to account for delays from the flash. TODO: Might not be required.
196 Reg#(Bit#(1)) tcen<-mkReg(0);
197 Reg#(Bit#(1)) cr_tcen =conditionalWrite(tcen,sr_busy==0); // enables the timeout counter.
198 Reg#(Bit#(1)) cr_dmaen <- mkReg(0); // enables the dma transfer.
199 Reg#(Bit#(1)) cr_abort <- mkReg(0); // this bit aborts the ongoing transaction.
200 Reg#(Bit#(1)) cr_en <-mkReg(0); // this bit enables the qspi.
201 Reg#(Bit#(32)) cr=concatReg19(cr_prescaler,cr_pmm,cr_apms,readOnlyReg(1'b0),cr_toie,cr_smie,cr_ftie,cr_tcie,cr_teie,readOnlyReg(4'd0),cr_fthres,cr_fsel,cr_dfm,readOnlyReg(1'b0),cr_sshift,cr_tcen,cr_dmaen,cr_abort,cr_en);
202
203 Reg#(Bit#(5)) fsize<-mkReg(0);
204 Reg#(Bit#(5)) dcr_fsize =conditionalWrite(fsize,sr_busy==0); // flash memory size.
205 Reg#(Bit#(3)) csht <-mkReg(0);
206 Reg#(Bit#(3)) dcr_csht = conditionalWrite(csht,sr_busy==0); // chip select high time.
207 Reg#(Bit#(1)) ckmode <-mkReg(0);
208 Reg#(Bit#(1)) dcr_ckmode =conditionalWrite(ckmode,sr_busy==0); // mode 0 or mode 3.
209 Reg#(Bit#(8)) dcr_mode_byte <- mkReg(0);
210 Reg#(Bit#(32)) dcr = concatReg7(readOnlyReg(3'd0),dcr_mode_byte,dcr_fsize,readOnlyReg(5'd0),dcr_csht,readOnlyReg(7'd0),dcr_ckmode);
211 Reg#(Bit#(32)) rg_mode_bytes = concatReg2(dcr_mode_byte,readOnlyReg(24'd0));
212 Reg#(Bit#(5)) rg_mode_byte_counter <- mkReg('d31);
213
214 Reg#(Bit#(1)) fcr_ctof <-mkReg(0); // writing 1 clears the sr_tof flag.
215 Reg#(Bit#(1)) fcr_csmf <-mkReg(0); // writing 1 clears the sr_smf flag.
216 Reg#(Bit#(1)) fcr_ctcf <-mkReg(0); // writing 1 clears the sr_tcf flag.
217 Reg#(Bit#(1)) fcr_ctef <-mkReg(0); // writing 1 clears the sr_tef flag.
218 Reg#(Bit#(32)) fcr=concatReg6(readOnlyReg(27'd0),clearSideEffect(fcr_ctof,sr_tof._write(0),noAction),clearSideEffect(fcr_csmf,sr_smf._write(0),noAction),readOnlyReg(1'b0),clearSideEffect(fcr_ctcf,sr_tcf._write(0),delay_sr_tcf._write(0)),clearSideEffect(fcr_ctef,sr_tef._write(0),noAction));
219
220 Reg#(Bit#(32)) data_length<-mkReg(0);
221 Reg#(Bit#(32)) dlr=conditionalWrite(data_length,sr_busy==0); // data length register
222
223 Reg#(Bit#(1)) ddrm<-mkReg(0);
224 Reg#(Bit#(1)) ccr_ddrm =conditionalWrite(ddrm,sr_busy==0); // double data rate mode.
225 Reg#(Bit#(1)) dhhc <-mkReg(0);
226 Reg#(Bit#(1)) ccr_dhhc =conditionalWrite(dhhc,sr_busy==0); // delay output by 1/4 in DDR mode. TODO: Not required.
227 Reg#(Bit#(1)) sioo <-mkReg(0);
228 Reg#(Bit#(1)) ccr_sioo =conditionalWrite(sioo,sr_busy==0); // send instruction based on mode selected.
229 Reg#(Bit#(2)) fmode <-mkReg(0);
230 Reg#(Bit#(2)) ccr_fmode =conditionalWrite(fmode,sr_busy==0); // 00: indirect Read, 01: indirect Write, 10: Auto polling, 11: MMapped.
231 Reg#(Bit#(2)) dmode <-mkReg(0);
232 Reg#(Bit#(2)) ccr_dmode =conditionalWrite(dmode,sr_busy==0); // data mode. 01: single line, 10: two line, 11: four lines.
233 Reg#(Bit#(5)) dcyc <-mkReg(0);
234 Reg#(Bit#(5)) ccr_dcyc =conditionalWrite(dcyc,sr_busy==0); // number of dummy cycles.
235 Reg#(Bit#(2)) absize <-mkReg(0);
236 Reg#(Bit#(2)) ccr_absize=conditionalWrite(absize,sr_busy==0); // number of alternate byte sizes.
237 Reg#(Bit#(2)) abmode <-mkReg(0);
238 Reg#(Bit#(2)) ccr_abmode=conditionalWrite(abmode,sr_busy==0); // alternate byte mode.
239 Reg#(Bit#(2)) adsize <-mkReg(0);
240 Reg#(Bit#(2)) ccr_adsize=conditionalWrite(adsize,sr_busy==0); // address size.
241 Reg#(Bit#(2)) admode <-mkReg(0);
242 Reg#(Bit#(2)) ccr_admode=conditionalWrite(admode,sr_busy==0); // address mode.
243 Reg#(Bit#(2)) imode <-mkReg(0);
244 Reg#(Bit#(2)) ccr_imode =conditionalWrite(imode,sr_busy==0); // instruction mode.
245 Reg#(Bit#(8)) instruction <-mkReg(0);
246 Reg#(Bit#(8)) ccr_instruction =conditionalWrite(instruction,sr_busy==0); // instruction to be sent externally.
247 Reg#(Bit#(1)) ccr_dummy_confirmation <- mkReg(0); //Programming Dummy confirmation bit needed by Micron model to trigger XIP mode
248 Reg#(Bit#(1)) ccr_dummy_bit <- mkReg(0); //Dummy bit to be sent
249 Reg#(Bit#(32)) ccr =writeCCREffect(concatReg14(ccr_ddrm,ccr_dhhc,ccr_dummy_bit,ccr_sioo,ccr_fmode,ccr_dmode,ccr_dummy_confirmation,ccr_dcyc,ccr_absize,ccr_abmode,ccr_adsize,ccr_admode,ccr_imode,ccr_instruction),wr_instruction_written._write(True),first_read._write(True));
250
251 Reg#(Bit#(32)) mm_data_length <-mkConfigReg(0);
252 Reg#(Bit#(28)) mm_address <-mkConfigReg(0);
253 Reg#(Bit#(28)) rg_prev_addr <- mkConfigReg(0);
254 Reg#(Bit#(32)) rg_address <-mkReg(0);
255 Reg#(Bit#(32)) ar =conditionalWrite(writeSideEffect(rg_address,wr_address_written._write(True)),sr_busy==0 && ccr_fmode!='b11); // address register
256
257 Reg#(Bit#(32)) rg_alternatebyte_reg<-mkReg(0);
258 Reg#(Bit#(32)) abr=conditionalWrite(rg_alternatebyte_reg,sr_busy==0); // alternate byte register
259
260 Reg#(Bit#(32)) rg_data <-mkReg(0);
261 Reg#(Bit#(32)) dr =writeSideEffect(rg_data,wr_data_written._write(True)); // data register
262
263 Reg#(Bit#(32)) rg_psmkr <-mkReg(0);
264 Reg#(Bit#(32)) psmkr =conditionalWrite(rg_psmkr,sr_busy==0); // polling status mask register
265
266 Reg#(Bit#(32)) rg_psmar <-mkReg(0);
267 Reg#(Bit#(32)) psmar =conditionalWrite(rg_psmar,sr_busy==0); // polling statue match register
268
269 Reg#(Bit#(16)) pir_interval <-mkReg(0); // polling interval
270 Reg#(Bit#(32)) pir =conditionalWrite(concatReg2(readOnlyReg(16'd0),pir_interval),sr_busy==0); // polling interval register
271
272 Reg#(Bit#(16)) lptr_timeout <-mkReg(0); // timeout period
273 Reg#(Bit#(32)) lptr =conditionalWrite(concatReg2(readOnlyReg(16'd0),lptr_timeout),sr_busy==0); // low power timeout register.
274 Reg#(Bool) thres <- mkReg(False);
275 Reg#(Bit#(32)) sdio0r <- mkReg(32'h00000073);
276 Reg#(Bit#(32)) sdio1r <- mkReg(32'h00000073);
277 Reg#(Bit#(32)) sdio2r <- mkReg(32'h00000073);
278 Reg#(Bit#(32)) sdio3r <- mkReg(32'h00000073);
279 Reg#(Bool) rg_request_ready <- mkReg(True);
280 Bool ddr_clock = ((wr_sdr_clock&&!wr_sdr_delayed)||(!wr_sdr_clock&&wr_sdr_delayed));
281 Bool transfer_cond = (sr_busy==1 && cr_abort==0 && cr_en==1);
282 Bool clock_cond = ((wr_sdr_clock && ccr_ddrm==0) || (ddr_clock && ccr_ddrm==1));
283 Bool qspi_flush = (cr_abort==1 || cr_en==0);
284 /*************** End of QSPI defined Registers *****************/
285 function Reg#(Bit#(32)) access_register(Bit#(8) address);
286 Reg#(Bit#(32)) register=(
287 case(address)
288 `CR : cr;
289 `DCR : dcr;
290 `FCR : fcr;
291 `DLR : dlr;
292 `CCR : ccr;
293 `AR : ar;
294 `ABR : abr;
295 `DR : dr;
296 `SR : sr;
297 `PSMKR : psmkr;
298 `PSMAR : psmar;
299 `PIR : pir;
300 `LPTR : lptr;
301 `SDIO0 : sdio0r;
302 `SDIO1 : sdio1r;
303 `SDIO2 : sdio2r;
304 `SDIO3 : sdio3r;
305 default: readOnlyReg(0);
306 endcase
307 );
308 return register;
309 endfunction
310
311 /* This function defines the next phase that needs to be executed. indicates if
312 the operation is over and also the value of rg_count_bits for the next phase*/
313 function Tuple3#(Bit#(32),Bit#(1),Phase) phase_change(Phase current_phase, Bit#(32) count_val, Bit#(1) smf);
314 Phase next_phase=Idle;
315 if(current_phase==Idle)
316 next_phase=Instruction_phase;
317 if(current_phase==Instruction_phase)
318 next_phase=Address_phase;
319 if(current_phase==Address_phase)
320 next_phase=AlternateByte_phase;
321 if(current_phase==AlternateByte_phase)
322 next_phase=Dummy_phase;
323 if(current_phase==Dummy_phase)
324 next_phase=(ccr_fmode=='b00)?DataWrite_phase:DataRead_phase;
325 if(current_phase==DataRead_phase)begin
326 if(ccr_fmode=='b01 || ccr_fmode=='b10) // indirect modes
327 next_phase=Idle;
328 else if(ccr_fmode=='b10) // auto-status polling mode
329 if(smf==1)
330 next_phase=Idle;
331 else
332 next_phase=Dummy_phase;
333 else
334 next_phase=DataRead_phase; //Memory Mapped mode
335 end
336 if(current_phase==DataWrite_phase)
337 next_phase=Idle;
338
339 if(next_phase==Instruction_phase && (ccr_imode==0||(ccr_sioo==1 && instruction_sent))) // if single instruction mode or no instruction mode
340 next_phase=Address_phase;
341 if(next_phase==Address_phase && ccr_admode==0)
342 next_phase=AlternateByte_phase;
343 if(next_phase==AlternateByte_phase && ccr_abmode==0)
344 next_phase=Dummy_phase;
345 if(next_phase==Dummy_phase && ccr_dcyc==0)
346 next_phase=ccr_fmode==0?DataWrite_phase:DataRead_phase;
347 if(next_phase==Dummy_phase && (ccr_fmode=='b10 && pir_interval==0))begin // TODO Check if this is correct or needs more logic.
348 next_phase=Instruction_phase;
349 end
350 if((next_phase==DataWrite_phase || next_phase==DataRead_phase) && ccr_dmode==0 && ccr_fmode!='b11)begin
351 if(ccr_fmode=='b01 || ccr_fmode=='b00)
352 next_phase=Idle;
353 else if(ccr_fmode=='b10)
354 if(smf==1)
355 next_phase=Idle;
356 else
357 next_phase=Dummy_phase;
358 end
359
360 if(next_phase==Instruction_phase)begin
361 count_val=8;
362 end
363 if(next_phase==Address_phase)begin
364 count_val=(ccr_fmode=='b11)?32:(case(ccr_adsize) 0:8; 1:16; 2:24; 3:32; endcase);
365 end
366 if(next_phase==AlternateByte_phase)begin
367 count_val=(case(ccr_absize) 0:8; 1:16; 2:24; 3:32; endcase);
368 end
369 if(next_phase==Dummy_phase)begin
370 count_val=(ccr_fmode=='b10)? zeroExtend(pir_interval):zeroExtend(ccr_dcyc);
371 end
372 if(next_phase==DataWrite_phase)begin
373 count_val=8;
374 end
375 if(next_phase==DataRead_phase)begin
376 count_val=0;
377 end
378 Bit#(1) tcf=0;
379 if(current_phase!=Idle && next_phase==Idle && (ccr_fmode=='b00 || ccr_fmode=='b01))begin // only in indirect mode raise completion of transfer TODO remove ccr_fmode=='b11 from this line.
380 tcf=1;
381 end
382 return tuple3(count_val,tcf,next_phase);
383 endfunction
384
385 Wrapper3#(Phase,Bit#(32),Bit#(1),Tuple3#(Bit#(32),Bit#(1),Phase)) change_phase<-mkUniqueWrapper3(phase_change);
386 /* This rule receives the write request from the AXI and updates the relevant
387 QSPI register set using the lower 12 bits as address map */
388 rule rl_write_request_from_AXI;
389 let aw <- pop_o (s_xactor.o_wr_addr);
390 let w <- pop_o (s_xactor.o_wr_data);
391 AXI4_Lite_Resp axi4_bresp = AXI4_LITE_OKAY;
392 if(ccr_fmode=='b11 && aw.awaddr[7:0]==`DR) begin //Undefined behavior when written into integral fields in CR, CCR!!!
393 axi4_bresp = AXI4_LITE_SLVERR;
394 `ifdef verbose $display("Sending AXI4_LITE_SLVERR because store in memory mapped mode and not clearing Interrupt Flags"); `endif
395 end
396 `ifdef verbose $display($time,"\tReceived AXI write request to Address: %h Data: %h Size: %h",aw.awaddr,w.wdata,aw.awsize); `endif
397 if(aw.awaddr[7:0]==`DR)begin
398 if(aw.awsize==0)begin
399 dr[7:0]<=w.wdata[7:0];
400 Vector#(4,Bit#(8)) temp=newVector();
401 temp[0]=w.wdata[7:0];
402 if(fifo.enqReadyN(1))
403 fifo.enq(1,temp);
404 end
405 else if(aw.awsize==1)begin
406 dr[15:0]<=w.wdata[15:0];
407 Vector#(4,Bit#(8)) temp = newVector();
408 temp[0]=w.wdata[7:0];
409 temp[1]=w.wdata[15:8];
410 if(fifo.enqReadyN(2))
411 fifo.enq(2,temp);
412 end
413 else if(aw.awsize==2)begin
414 dr<=w.wdata[31:0];
415 Vector#(4,Bit#(8)) temp = newVector();
416 temp[3]=w.wdata[31:24];
417 temp[2]=w.wdata[23:16];
418 temp[1]=w.wdata[15:8];
419 temp[0]=w.wdata[7:0];
420 if(fifo.enqReadyN(4))
421 fifo.enq(4,temp);
422 end
423 else begin
424 axi4_bresp = AXI4_LITE_SLVERR;
425 `ifdef verbose $display("Sending AXI4_LITE_SLVERR because DR awsize is 64-bit"); `endif
426 end
427 end
428 else begin
429 let reg1=access_register(aw.awaddr[7:0]);
430 `ifdef verbose $display("Write Reg access: %h Write Data: %h Size: %h",aw.awaddr[7:0],w.wdata,aw.awsize); `endif
431 //Byte and Half-Word Writes are not permitted in ConfigReg Space
432 if(aw.awsize==2) // 32 bits
433 reg1<=w.wdata[31:0];
434 else begin
435 axi4_bresp = AXI4_LITE_SLVERR;
436 `ifdef verbose $display("Sending SLVERR because Accessed register's awsize was different"); `endif
437 end
438 end
439
440 let b = AXI4_Lite_Wr_Resp {bresp: axi4_bresp, buser: aw.awuser};
441 s_xactor.i_wr_resp.enq (b);
442 endrule
443
444 /* This rule receives the read request from the AXI and responds with the relevant
445 QSPI register set using the lower 12 bits as address map */
446 (*descending_urgency="rl_read_request_from_AXI,rl_write_request_from_AXI"*) //experimental
447 rule rl_read_request_from_AXI(rg_request_ready==True);
448 let axir<- pop_o(s_xactor.o_rd_addr);
449 Bool request_ready = True;
450 `ifdef verbose $display($time,"\tReceived AXI read request to Address: %h Size: %h",axir.araddr,axir.arsize); `endif
451 if((axir.araddr[27:0]>=`STARTMM && axir.araddr[27:0]<=`ENDMM) && axir.araddr[31]==1'b1)begin // memory mapped space
452
453 wr_read_request_from_AXI<=True; //Could this lead to some error? Need to think about this, without fail
454 AXI4_Lite_Resp axi4_rresp = AXI4_LITE_OKAY;
455 mm_address<=truncate(axir.araddr);
456 Bit#(4) data_length = axir.arsize==0?1:axir.arsize==1?2:axir.arsize==2?4:8;
457 mm_data_length<= zeroExtend(data_length);
458 Bit#(28) address_limit = 1 << dcr_fsize;
459
460 //It is forbidden to access the flash bank area before the SPI is properly configured -- fmode is '11??
461 //If not sending a SLVERR now if the mode is not memory mapped and if an access is made outside allowed
462 if(ccr_fmode!='b11 || axir.araddr[27:0] > address_limit) begin
463 `ifdef verbose $display("Sending Slave Error ccr_fmode: %h mm_address: %h address_limit: %h dcr_fsize: %h",ccr_fmode,mm_address,address_limit, dcr_fsize); `endif
464 axi4_rresp = AXI4_LITE_SLVERR;
465 let r = AXI4_Lite_Rd_Data {rresp: axi4_rresp, rdata: 0 , ruser: 0};
466 s_xactor.i_rd_data.enq(r);
467 axi4_rresp = AXI4_LITE_SLVERR;
468 rg_phase <= Idle; //Will this work?
469 cr_en <= 0;
470 sr_busy <= 0;
471 ncs <= 1; //Just resetting all the parameters, just in case. Should Ask Neel
472 first_read <= True;
473 end
474 else if(sr_busy==1 ||thres) begin //Bus is busy with Memory mapped maybe?
475 `ifdef verbose $display($time,"sr_busy: %d, thres: %d rg_prev_addr: %h axir.araddr: %h fifo_count: %d", sr_busy, thres, rg_prev_addr, axir.araddr, fifo.count); `endif
476 Bit#(28) eff_addr = rg_prev_addr + zeroExtend(data_length);
477 if((eff_addr!= truncate(axir.araddr)) || pack(fifo.count)==0 || ccr_dummy_bit==1'b1) begin
478 `ifdef verbose $display($time,"Not Equal eff_addr: %h mm_address : %h axir.araddr: %h rg_prev_addr: %h data_length : %h sum : %h fifo.count: %h ccr_dummy_bit: %h",eff_addr,mm_address,axir.araddr,rg_prev_addr,data_length,rg_prev_addr+zeroExtend(data_length),pack(fifo.count),ccr_dummy_bit); `endif
479 sr_busy<=0;
480 rg_phase<=Idle;
481 ncs<=1;
482 fifo.clear();
483 thres <= False;
484 //$display($time,"Setting Thres to FALSE");
485 first_read <= True;
486 request_ready = False;
487 end
488 else if(!first_read) begin
489 request_ready = True;
490 rg_prev_addr <= truncate(axir.araddr);
491 Bit#(32) reg1 = 0;
492 if(axir.arsize==0) begin // 8 bits
493 if(fifo.deqReadyN(1))begin
494 let temp=fifo.first[0];
495 reg1=duplicate(temp);
496 fifo.deq(1);
497 end
498 end
499 else if(axir.arsize==1) begin // 16 bits
500 if(fifo.deqReadyN(2)) begin
501 let temp={fifo.first[0],fifo.first[1]};
502 reg1=duplicate(temp);
503 fifo.deq(2);
504 end
505 end
506 else if(axir.arsize==2) begin // 32 bits
507 if(fifo.deqReadyN(4)) begin
508 let temp={fifo.first[0],fifo.first[1],fifo.first[2],fifo.first[3]};
509 reg1=duplicate(temp);
510 fifo.deq(4);
511 end
512 end
513 else
514 axi4_rresp = AXI4_LITE_SLVERR;
515 `ifdef verbose $display("Sending Response to the core: reg1: %h", reg1); `endif
516 let r = AXI4_Lite_Rd_Data {rresp: axi4_rresp, rdata: duplicate(reg1) , ruser: 0};
517 s_xactor.i_rd_data.enq(r);
518 end
519 end
520 end
521 else begin
522 let reg1=access_register(axir.araddr[7:0]);
523 `ifdef verbose $display("Reg Read Access: %h arsize: %h",axir.araddr[7:0], axir.arsize); `endif
524 if(axir.araddr[7:0]==`SR)
525 wr_status_read<=True;
526 if(axir.araddr[7:0]==`DR)begin // accessing the data register for read.
527 `ifdef verbose $display("Accessed DR fifo_count : %d axi.arsize: %d", fifo.count, axir.arsize); `endif
528 if(ccr_fmode=='b10)
529 wr_data_read<=True;
530 if(axir.arsize==0) begin // 8 bits
531 if(fifo.deqReadyN(1))begin
532 let temp=fifo.first[0];
533 reg1=duplicate(temp);
534 fifo.deq(1);
535 end
536 end
537 else if(axir.arsize==1) begin // 16 bits
538 if(fifo.deqReadyN(2)) begin
539 let temp={fifo.first[0],fifo.first[1]};
540 reg1=duplicate(temp);
541 fifo.deq(2);
542 end
543 end
544 else /*if(axir.arsize==2)*/ begin // 32 bits -- Even if the request is a long int, respond with int since that's the max we can do
545 if(fifo.deqReadyN(4)) begin
546 let temp={fifo.first[0],fifo.first[1],fifo.first[2],fifo.first[3]};
547 reg1=duplicate(temp);
548 fifo.deq(4);
549 end
550 end
551 end
552 `ifdef verbose $display("Sending Response : reg1: %x", reg1); `endif
553 let r = AXI4_Lite_Rd_Data {rresp: AXI4_LITE_OKAY, rdata: duplicate(reg1) ,ruser: 0};
554 request_ready = True;
555 s_xactor.i_rd_data.enq(r);
556 end
557 rg_request_ready <= request_ready;
558 `ifdef verbose $display($time,"QSPI: Is Request ready? : %h",request_ready); `endif
559 endrule
560
561
562 rule timeout_counter;
563 if(cr_tcen==1 && sr_tof==0) // timecounter is enabled
564 if(timecounter==lptr_timeout[15:0])begin
565 timecounter<=0;
566 sr_tof<=1;
567 end
568 else
569 timecounter<=timecounter+1;
570 endrule
571
572 rule delayed_sr_tcf_signal(transfer_cond &&
573 ((ccr_ddrm==1 && ddr_clock && (ccr_admode!=0 || ccr_dmode!=0)) || wr_sdr_clock));
574 sr_tcf<=delay_sr_tcf;
575 endrule
576
577 rule delayed_ncs_generation;
578 delay_ncs<=ncs;
579 endrule
580
581 rule delay_sdr;
582 wr_sdr_delayed <= wr_sdr_clock;
583 endrule
584
585
586 /* This rule generates the clk signal. The Prescaler register defines the
587 division factor wrt to the Global clock. The prescaler will only work when the
588 chip select is low i.e when the operation has been initiated. */
589 rule rl_generate_clk_from_master;
590 if(delay_ncs==1)begin
591 rg_clk_counter<=0;
592 rg_clk<=dcr_ckmode;
593 `ifdef verbose1 $display("dcr_ckmode: %h",dcr_ckmode); `endif
594 end
595 else begin
596 let half_clock_value=cr_prescaler>>1;
597 if(cr_prescaler[0]==0)begin // odd division
598 if(rg_clk_counter<=half_clock_value)
599 rg_clk<=0;
600 else
601 rg_clk<=1;
602 if(rg_clk_counter==cr_prescaler)
603 rg_clk_counter<=0;
604 else
605 rg_clk_counter<=rg_clk_counter+1;
606 if(rg_clk_counter == half_clock_value || rg_clk_counter==cr_prescaler)begin
607 wr_sdr_clock<=rg_phase==DataRead_phase?unpack(~rg_clk):unpack(rg_clk);
608 end
609 end
610 else begin // even division
611 if(rg_clk_counter==half_clock_value)begin
612 rg_clk<=~rg_clk;
613 rg_clk_counter<=0;
614 wr_sdr_clock<=rg_phase==DataRead_phase?unpack(~rg_clk):unpack(rg_clk);
615 end
616 else if(delay_ncs==0)
617 rg_clk_counter<=rg_clk_counter+1;
618 end
619 end
620 endrule
621
622 /* update the status flag on each cycle */
623 rule rl_update_fifo_level;
624 sr_flevel<=pack(fifo.count);
625 endrule
626 /* set the fifo threshold flag when the FIFO level is equal to the FTHRESH value */
627 (*preempts="rl_set_busy_signal,rl_update_threshold_flag"*)
628 rule rl_update_threshold_flag;
629 if(ccr_fmode=='b00)begin// indirect write mode
630 sr_ftf<=pack(16-pack(fifo.count)>={1'b0,cr_fthres}+1);
631 end
632 else if(ccr_fmode=='b01) begin
633 sr_ftf<=pack(pack(fifo.count)>=({1'b0,cr_fthres}+1));
634 `ifdef verbose1 $display("fifo count: %d fthres: %d",fifo.count,cr_fthres); `endif
635 end
636 else if(ccr_fmode=='b10 && wr_status_read)begin // auto_status polling mode
637 sr_ftf<=1;
638 end
639 else if(ccr_fmode=='b10 && wr_data_read)begin // auto_status polling mode
640 sr_ftf<=0;
641 end
642 else if(ccr_fmode=='b11 && pack(fifo.count)>={1'b0,cr_fthres}+1) begin
643 ncs<=1;
644 sr_busy<=0;
645 rg_phase<=Idle; // Will this work?
646 thres<= True;
647 rg_request_ready <= True;
648 // $display($time,"THRES is being set to TRUE kyaaaa?");
649 end
650 endrule
651
652 /* If abort is raised or the QSPI is disabled go back to Idle Phase*/
653 //(*descending_urgency = "if_abort,rl_read_request_from_AXI"*)
654 //(*descending_urgency = "if_abort,rl_write_request_from_AXI"*)
655 (*preempts = "if_abort,rl_update_threshold_flag"*)
656 rule if_abort(qspi_flush);
657 //$display("Received Abort or Disable request, going to idle");
658 rg_phase<=Idle;
659 ncs <= 1;
660 sr_busy <= 0;
661 thres <= False;
662 read_true <= False;
663 first_read <= False;
664 instruction_sent <= False;
665 half_cycle_delay <= False;
666 fifo.clear(); //What if its already empty? clearing the fifo, so doesn't matter
667 endrule
668
669 /*operate the busy signal in different mode */
670 rule rl_reset_busy_signal(sr_busy==1);
671 if(cr_abort==1)begin
672 sr_busy<=0;
673 ncs<=1;
674 end
675 else if(ccr_fmode=='b00 || ccr_fmode=='b01)begin // indirect write or read mode;
676 if(/*fifo.count==0 &&*/ sr_tcf==1)begin // if FIFO is empty and the transaction is complete
677 sr_busy<=0;
678 ncs<=1;
679 end
680 end
681 else if(ccr_fmode=='b10)begin // automatic polling mode
682 if(sr_smf==1)begin
683 sr_busy<=0;
684 ncs<=1;
685 end
686 end
687 else if(ccr_fmode=='b11)begin
688 if(sr_tof==1 || cr_en==0 || cr_abort==1) begin// timeout event
689 sr_busy<=0;
690 ncs<=1;
691 end
692 end
693 endrule
694 (*descending_urgency="rl_set_busy_signal,rl_read_request_from_AXI"*)
695 (*descending_urgency="rl_set_busy_signal,rl_write_request_from_AXI"*)
696 rule rl_set_busy_signal(sr_busy==0 && rg_phase==Idle && cr_abort==0 && cr_en==1);
697 rg_output_en<=0;
698 instruction_sent<=False;
699 `ifdef verbose1 $display($time,"\tWaiting for change in phase wr_read_request_from_AXI: %b ccr_fmode: %h thres: %h",wr_read_request_from_AXI,ccr_fmode,thres); `endif
700 if(wr_instruction_written)begin
701 sr_busy<=1;
702 ncs<=0;
703 rg_phase<=Instruction_phase;
704 rg_count_bits<=8;
705 end
706 else if((wr_address_written && ccr_admode!=0 && (ccr_fmode=='b01 || ccr_dmode=='d0 || ccr_fmode=='b10))|| (wr_data_written && ccr_admode!=0 && ccr_dmode!=0 && ccr_fmode=='b00))begin
707 sr_busy<=1; // start some transaction
708 `ifdef verbose $display("Address Written and going to Some mode"); `endif
709 ncs<=0;
710 let {x,y,z}<-change_phase.func(rg_phase,0,0);
711 rg_count_bits<=x;
712 rg_count_bytes<=0;
713 rg_phase<=z;
714 `ifdef verbose $display("Mode is :",fshow(z),"Count_bits : %d",x); `endif
715 if(z==DataRead_phase)
716 read_true <= True;
717 end
718 else if(wr_read_request_from_AXI && ccr_fmode=='b11 && !thres)begin // memory-mapped mode.
719 `ifdef verbose $display("Entering Memory mapped mode"); `endif
720 sr_busy<=1;
721 ncs<=0;
722 let {x,y,z}<-change_phase.func(rg_phase,0,0);
723 rg_count_bits<=x;
724 rg_count_bytes<=0;
725 rg_phase<=z;
726 `ifdef verbose $display("rg_phase :",fshow(z)); `endif
727 if(z==DataRead_phase)
728 read_true <= True;
729 end
730 endrule
731
732 /* This rule generates the error signal interrupt in different scenarios */
733 rule set_error_signal;
734 Bit#(32) actual_address=1<<(dcr_fsize);
735 if(wr_address_written && ar>actual_address && (ccr_fmode=='b00 || ccr_fmode=='b01))
736 sr_tef<=1;
737 else if(wr_address_written && ar+dlr>actual_address &&(ccr_fmode=='b00 || ccr_fmode=='b01))
738 sr_tef<=1;
739 else if(wr_address_written)
740 sr_tef<=0;
741 endrule
742
743 /* Rule to transfer the instruction of 8-bits outside. THe size of instruction is fixed
744 to 8 bits by protocol. Instruction phase will always be in SDR mode */
745 rule rl_transfer_instruction(rg_phase==Instruction_phase && transfer_cond && wr_sdr_clock && !qspi_flush);
746 Bool end_of_phase=False;
747 let reverse_instruction=ccr_instruction;
748 let count_val=rg_count_bits;
749 `ifdef verbose1 $display("Executing Instruction Phase SPI Mode: %b Count_bits: %d InstructionReverse: %h",ccr_imode,rg_count_bits,reverse_instruction); `endif
750 Bit#(4) enable_o=0;
751 if(ccr_imode=='b01)begin // single spi mode;
752 enable_o=4'b1101;
753 rg_output<={1'b1,1'b0,1'b0,reverse_instruction[rg_count_bits-1]};
754 if(rg_count_bits==1)begin// end of instruction stream
755 end_of_phase=True;
756 end
757 else
758 count_val=rg_count_bits-1;
759 end
760 else if (ccr_imode=='b10)begin // dual mode;
761 enable_o=4'b1111;
762 rg_output<={1'b1,1'b0,reverse_instruction[rg_count_bits-1:rg_count_bits-2]};
763 if(rg_count_bits==2)begin// end of instruction stream
764 end_of_phase=True;
765 end
766 else
767 count_val=rg_count_bits-2;
768 end
769 else if (ccr_imode=='b11)begin // quad mode;
770 enable_o=4'b1111;
771 rg_output<=reverse_instruction[rg_count_bits-1:rg_count_bits-4];
772 if(rg_count_bits==4)begin// end of instruction stream
773 end_of_phase=True;
774 end
775 else
776 count_val=rg_count_bits-4;
777 end
778 if(end_of_phase || ccr_imode==0)begin // end of instruction or no instruction phase
779 let {x,y,z}<-change_phase.func(rg_phase,count_val,0);
780 instruction_sent<=True;
781 rg_count_bits<=x;
782 delay_sr_tcf<=y;
783 rg_phase<=z;
784 rg_count_bytes<=0;
785 if(ccr_ddrm==1)
786 half_cycle_delay<=True;
787 if(z==DataRead_phase)
788 read_true <= True;
789 end
790 else
791 rg_count_bits<=count_val;
792 rg_output_en<=enable_o;
793 endrule
794
795 /* Rule to transfer the address bits of address outside. The size of address is
796 defined by the ccr_adsize register in ccr */
797 rule rl_transfer_address(rg_phase==Address_phase && transfer_cond && clock_cond && !qspi_flush);
798 if(half_cycle_delay) begin
799 half_cycle_delay<=False;
800 read_true <= True; //A workaround for the delay .. For DDR mode, the clock should be pushed one cycle and not half
801 end
802 else if(read_true)
803 read_true <= False;
804 else begin
805 Bool end_of_phase=False;
806 Bit#(4) enable_o=0;
807 let count_val=rg_count_bits;
808 Bit#(32) address=(ccr_fmode=='b11)?zeroExtend(mm_address):ar;
809 rg_prev_addr <= truncate(address);
810 `ifdef verbose1 $display($time,"Executing Address Phase SPI Mode: %b Address Size: %d Count_bits: %d Address: %b",ccr_admode,ccr_adsize,rg_count_bits,address); `endif
811 if(ccr_admode=='b01)begin // single spi mode;
812 enable_o=4'b1101;
813 rg_output<={1'b1,1'b0,1'b0,address[rg_count_bits-1]};
814 `ifdef verbose $display($time,"Single: Sending Address bit %h bit_number: %d total_address: %h",rg_count_bits-1,address[rg_count_bits-1],address); `endif
815 if(rg_count_bits==1)begin// end of address stream
816 end_of_phase=True;
817 end
818 else
819 count_val=rg_count_bits-1;
820 end
821 else if (ccr_admode=='b10)begin // dual mode;
822 enable_o=4'b1111;
823 rg_output<={1'b1,1'b0,address[rg_count_bits-1:rg_count_bits-2]};
824 `ifdef verbose $display($time,"Double: Sending Address bit %h bit_number: %d total_address: %h",rg_count_bits-1,address[rg_count_bits-1],address); `endif
825 if(rg_count_bits==2)begin// end of address stream
826 end_of_phase=True;
827 end
828 else
829 count_val=rg_count_bits-2;
830 end
831 else if (ccr_admode=='b11)begin // quad mode;
832 enable_o=4'b1111;
833 rg_output<=address[rg_count_bits-1:rg_count_bits-4];
834 `ifdef verbose $display($time,"Quad: Sending Address bit %h bit_number: %d total_address: %h",rg_count_bits-1,address[rg_count_bits-1],address); `endif
835 if(rg_count_bits==4)begin// end of address stream
836 end_of_phase=True;
837 end
838 else
839 count_val=rg_count_bits-4;
840 end
841 if(end_of_phase || ccr_admode==0)begin // end of address phase
842 let {x,y,z}<-change_phase.func(rg_phase,count_val,0);
843 rg_count_bits<=x;
844 delay_sr_tcf<=y;
845 rg_phase<=z;
846 rg_count_bytes<=0;
847 if(z==DataRead_phase)
848 read_true <= True;
849 end
850 else
851 rg_count_bits<=count_val;
852 rg_output_en<=enable_o;
853 end
854 endrule
855
856 /* Rule to transfer the alternate bytes. The size of alternate bytes is
857 defined by the ccr_absize register in ccr */
858 rule rl_transfer_alternatebytes(rg_phase==AlternateByte_phase && transfer_cond && clock_cond && !qspi_flush);
859 Bool end_of_phase=False;
860 let count_val=rg_count_bits;
861 `ifdef verbose1 $display("Executing AltByte Phase SPI Mode: %b AltByte Size: %d Count_bits: %d AltByte: %b",ccr_abmode,ccr_absize,rg_count_bits,abr); `endif
862 Bit#(4) enable_o=0;
863 if(ccr_abmode=='b01)begin // single spi mode;
864 enable_o=4'b1101;
865 rg_output<={1'b1,1'b0,1'b0,abr[rg_count_bits-1]};
866 if(rg_count_bits==1)begin// end of instruction stream
867 end_of_phase=True;
868 end
869 else
870 count_val=rg_count_bits-1;
871 end
872 else if (ccr_abmode=='b10)begin // dual mode;
873 enable_o=4'b1111;
874 rg_output<={1'b1,1'b0,abr[rg_count_bits-1:rg_count_bits-2]};
875 if(rg_count_bits==2)begin// end of instruction stream
876 end_of_phase=True;
877 end
878 else
879 count_val=rg_count_bits-2;
880 end
881 else if (ccr_abmode=='b11)begin // quad mode;
882 enable_o=4'b1111;
883 rg_output<=abr[rg_count_bits-1:rg_count_bits-4];
884 if(rg_count_bits==4)begin// end of instruction stream
885 end_of_phase=True;
886 end
887 else
888 count_val=rg_count_bits-4;
889 end
890 if(end_of_phase || ccr_abmode==0)begin // end of alternate byte phase
891 let {x,y,z}<-change_phase.func(rg_phase,count_val,0);
892 rg_count_bits<=x;
893 delay_sr_tcf<=y;
894 rg_phase<=z;
895 rg_count_bytes<=0;
896 if(z==DataRead_phase)
897 read_true <= True;end
898 else
899 rg_count_bits<=count_val;
900 rg_output_en<=enable_o;
901 endrule
902
903
904 rule rl_transfer_dummy_cycle(rg_phase==Dummy_phase && transfer_cond && wr_sdr_clock && !qspi_flush);
905 let {x,y,z} <- change_phase.func(rg_phase,rg_count_bits,0);
906 Bit#(5) count_val = rg_mode_byte_counter;
907 Bit#(4) enable_o = rg_output_en;
908 `ifdef verbose $display("\t Executing Dummy Phase: rg_mode_bytes: %b rg_mode_byte_counter: %d",rg_mode_bytes, rg_mode_byte_counter); `endif
909 if(ccr_dmode==1) begin
910 if(ccr_dummy_confirmation==1) begin
911 //rg_output_en <= 4'b1101;
912 enable_o = 4'b1101;
913 rg_output <= {1'b1,1'b0,1'b0,rg_mode_bytes[rg_mode_byte_counter]};
914 if(count_val!=0)
915 count_val = count_val - 1;
916 else
917 enable_o = 4'b0000;
918 end
919 else begin
920 //rg_output_en <= 4'b1101;
921 enable_o = 4'b1101;
922 rg_output <= {1'b1,1'b0,1'b0,1'b0};
923 end
924 end
925 else if(ccr_dmode==2) begin
926 if(ccr_dummy_confirmation==1) begin
927 //rg_output_en <= 4'b1111;
928 enable_o = 4'b1111;
929 rg_output <= {1'b1,1'b0,rg_mode_bytes[rg_mode_byte_counter:rg_mode_byte_counter-1]};
930 if(count_val!=0)
931 count_val = count_val - 2;
932 else
933 enable_o = 4'b0000;
934 end
935 else begin
936 //rg_output_en <= 4'b1100;
937 enable_o = 4'b1100;
938 rg_output <= {1'b1,1'b0,1'b0,1'b0};
939 end
940 end
941 else begin
942 if(ccr_dummy_confirmation==1) begin
943 //rg_output_en <= 4'b1111;
944 enable_o = 4'b1111;
945 rg_output <= rg_mode_bytes[rg_mode_byte_counter:rg_mode_byte_counter-3];
946 if(count_val!=3)
947 count_val = count_val - 4;
948 else
949 enable_o = 4'b0000;
950 end
951 else begin
952 //rg_output_en <= 4'b0000;
953 enable_o = 4'b0000;
954 end
955 end
956 if(rg_count_bits==0 || (rg_count_bits==1 && z!=DataRead_phase))begin // end of dummy cycles;
957 delay_sr_tcf<=y;
958 rg_phase<=z;
959 `ifdef verbose $display("From Dummy to :",fshow(z)); `endif
960 if(z==DataRead_phase)
961 read_true <= True;
962 rg_count_bytes<=0;
963 rg_count_bits<=x;
964 rg_mode_byte_counter <= 'd-1; //All ones
965 if(ccr_ddrm==1)
966 half_cycle_delay<=True;
967 end
968 else begin
969 rg_count_bits<=rg_count_bits-1;
970 rg_mode_byte_counter <= count_val;
971 rg_output_en <= enable_o;
972 end
973 endrule
974
975
976 /* Rule to transfer the dummy_cycles. The size of dummy cycles is
977 defined by the ccr_dcyc register in ccr. The number of dummy cycles should be calculated of
978 the complete cycle even in DDR mode hence using sdr clock*/
979 /* rule rl_transfer_dummy_cycle(rg_phase==Dummy_phase && transfer_cond && wr_sdr_clock && !qspi_flush);
980 let {x,y,z}<-change_phase.func(rg_phase,rg_count_bits,0);
981 `ifdef verbose $display($time,"Executing Dummy Phase, Dummy_confirmation_bit : %d dummy_bit : %d", ccr_dummy_confirmation, ccr_dummy_bit); `endif
982 if(ccr_dmode==1) begin
983 if(ccr_dummy_confirmation==1) begin
984 rg_output_en <= 4'b1101;
985 rg_output <= {1'b1,1'b0,1'b0,ccr_dummy_bit};
986 ccr_dummy_confirmation<=0;
987 end
988 else begin
989 rg_output_en <= 4'b1101;
990 rg_output <= {1'b1,1'b0,1'b0,1'b0};
991 end
992 end
993 else if(ccr_dmode==2) begin
994 if(ccr_dummy_confirmation==1) begin
995 rg_output_en <= 4'b1101;
996 rg_output <= {1'b1,1'b0,1'b0,ccr_dummy_bit};
997 ccr_dummy_confirmation <= 0;
998 end
999 else begin
1000 rg_output_en <= 4'b1100;
1001 rg_output <= {1'b1,1'b0,1'b0,1'b0};
1002 end
1003 end
1004 else begin
1005 if(ccr_dummy_confirmation==1) begin
1006 `ifdef verbose $display("Data going to output %d", ccr_dummy_bit); `endif
1007 rg_output_en <= 1;
1008 rg_output[0] <= ccr_dummy_bit;
1009 ccr_dummy_confirmation<=0;
1010 end
1011 else
1012 rg_output_en <= 0;
1013 end
1014 if(rg_count_bits==0 || (rg_count_bits==1 && z!=DataRead_phase))begin // end of dummy cycles;
1015 delay_sr_tcf<=y;
1016 rg_phase<=z;
1017 `ifdef verbose $display("From Dummy to :",fshow(z)); `endif
1018 if(z==DataRead_phase)
1019 read_true <= True;
1020 rg_count_bytes<=0;
1021 rg_count_bits<=x;
1022 if(ccr_ddrm==1)
1023 half_cycle_delay<=True;
1024 end
1025 else begin
1026 rg_count_bits<=rg_count_bits-1;
1027 end
1028 endrule*/
1029
1030 /* read data from the flash memory and store it in the DLR register. Simulataneously
1031 put Bytes in the FIFO*/
1032 (*descending_urgency="rl_data_read_phase,rl_read_request_from_AXI"*)
1033 (*descending_urgency="rl_data_read_phase,rl_write_request_from_AXI"*)
1034 rule rl_data_read_phase(rg_phase==DataRead_phase /*&& ccr_fmode!='b11*/ && transfer_cond && clock_cond && !qspi_flush);
1035 //rg_output_en<=0;
1036 if(half_cycle_delay || read_true) begin
1037 half_cycle_delay<=False;
1038 read_true <= False;
1039 end
1040 else begin
1041 Bit#(32) data_reg=dr;
1042 Bit#(32) count_byte=rg_count_bytes;
1043 Bit#(32) count_bits=rg_count_bits;
1044 Bit#(32) data_length1=(ccr_fmode=='b11)?mm_data_length:dlr;
1045 `ifdef verbose1 $display($time,"Executing DataRead Phase SPI Mode: %b DLR : %d Count_bits: %d Input :%b ccr_ddrm: %b",ccr_dmode,data_length1,rg_count_bits,rg_input,ccr_ddrm); `endif
1046 /* write incoming bit to the data register */
1047 if(ccr_dmode==1)begin // single line mode;
1048 data_reg=data_reg<<1;
1049 data_reg[0]=rg_input[1];
1050 `ifdef verbose $display($time,"Single data_reg : %b",data_reg); `endif
1051 count_bits=count_bits+1;
1052 rg_output_en <= 4'b1101;
1053 rg_output <= {1'b1,1'b0,1'b0,1'b0};
1054
1055 end
1056 else if(ccr_dmode==2)begin // dual line mode;
1057 rg_output_en <= 4'b1100;
1058 data_reg=data_reg<<2;
1059 data_reg[1:0]=rg_input[1:0];
1060 `ifdef verbose $display($time,"Dual data_reg : %b",data_reg); `endif
1061 count_bits=count_bits+1;
1062 rg_output <= {1'b1,1'b0,1'b0,1'b0};
1063 end
1064 else if(ccr_dmode==3) begin// quad line mode;
1065 rg_output_en <= 4'b0000;
1066 data_reg=data_reg<<4;
1067 data_reg[3:0]=rg_input;
1068 `ifdef verbose $display($time,"Quad data_reg : %b",data_reg); `endif
1069 count_bits=count_bits+1;
1070 end
1071
1072 /* write the last successfully received byte into the FIFO */
1073 if(ccr_dmode==1)begin// single line mode
1074 if(count_byte==data_length-1 && ccr_ddrm==1 && count_bits[2:0]=='b111) //To make sure that the Flash does not send any data the next half edge since ncs is made 1 after the second edge
1075 ncs<=1;
1076 if(rg_count_bits[2:0]=='b111)begin // multiple of eight bits have been read.
1077 `ifdef verbose1 $display("Enquing FIFO"); `endif
1078 Vector#(4,Bit#(8)) temp = newVector();
1079 temp[0]=data_reg[7:0];
1080 `ifdef verbose $display($time,"Single Enqueing FIFO : data is %h",temp[0]); `endif
1081 if(!first_read)
1082 fifo.enq(1,temp);
1083 count_byte=count_byte+1;
1084 end
1085 end
1086 else if(ccr_dmode==2) begin // dual line mode
1087 if(count_byte==data_length-1 && ccr_ddrm==1 && count_bits[1:0]=='b11) //To make sure that the Flash does not send any data the next half edge since ncs is made 1 after the second edge
1088 ncs<=1;
1089 if(rg_count_bits[1:0]=='b11)begin // multiple of eight bits have been read.
1090 `ifdef verbose1 $display("Enquing FIFO"); `endif
1091 Vector#(4,Bit#(8)) temp = newVector();
1092 temp[0]=data_reg[7:0];
1093 `ifdef verbose $display($time,"Dual Enqueing FIFO : data is %h",temp[0]); `endif
1094 if(!first_read)
1095 fifo.enq(1,temp);
1096 count_byte=count_byte+1;
1097 end
1098 end
1099 else if(ccr_dmode==3) begin // quad line mode
1100 if(count_byte==data_length-1 && ccr_ddrm==1 && count_bits[0]=='b1) //To make sure that the Flash does not send any data the next half edge since ncs is made 1 after the second edge
1101 ncs<=1;
1102 if(rg_count_bits[0]=='b1)begin // multiple of eight bits have been read.
1103 `ifdef verbose1 $display("Enquing FIFO"); `endif
1104 Vector#(4,Bit#(8)) temp = newVector();
1105 temp[0]=data_reg[7:0];
1106 `ifdef verbose $display($time,"Quad Enqueing FIFO : data is %h",temp[0]); `endif
1107 if(!first_read)
1108 fifo.enq(1,temp);
1109 count_byte=count_byte+1;
1110 end
1111 end
1112
1113 bit smf=0;
1114 `ifdef verbose $display("count_byte: %d data_length1: %d",count_byte,data_length1); `endif
1115 /* condition for termination of dataread_phase */
1116 if(data_length1!='hFFFFFFFF)begin // if limit is not undefined
1117 if(count_byte==data_length1)begin // if limit has bee reached.
1118 `ifdef verbose $display($time,"Limit has reached: rg_count_bytes %h data_length %h",count_byte,data_length); `endif
1119 if(ccr_fmode=='b10)begin // auto-status polling mode
1120 if(cr_pmm==0)begin // ANDed mode
1121 if((psmar&psmkr) == (psmkr&dr)) // is the unmasked bits match
1122 smf=1;
1123 else
1124 smf=0;
1125 end
1126 else begin// ORed mode
1127 let p=psmkr&dr;
1128 let q=psmkr&psmar;
1129 let r=~(p^q);
1130 if(|(r)==1)
1131 smf=1;
1132 else
1133 smf=0;
1134 end
1135 end
1136 else if(ccr_fmode=='b11)begin// memory mapped mode
1137 if(first_read) begin
1138 `ifdef verbose $display("Sending response back to the proc data_reg: %h",data_reg); `endif
1139 let r = AXI4_Lite_Rd_Data {rresp: AXI4_LITE_OKAY, rdata: duplicate(data_reg) , ruser: 0};
1140 s_xactor.i_rd_data.enq(r);
1141 first_read <= False;
1142 //rg_request_ready <= True;
1143 end
1144 end
1145 let {x,y,z}<-change_phase.func(rg_phase,rg_count_bits,smf);
1146 /* if(z==DataRead_phase)
1147 read_true <= True;*/
1148 rg_phase<=z;
1149 `ifdef verbose $display("rg_phase:",fshow(z),"sr_tcf: %d",y); `endif
1150 sr_tcf<=y; // set completion of transfer flag
1151 rg_count_bytes<=0;
1152 rg_count_bits<=0;
1153 end
1154 else begin
1155 rg_count_bytes<=count_byte;
1156 rg_count_bits<=count_bits;
1157 end
1158 end
1159 else if(dcr_fsize!='h1f)begin // if limit is not infinite
1160 Bit#(32) new_limit=1<<(dcr_fsize);
1161 `ifdef verbose1 $display("Sending completion -- newlimit : %h",new_limit); `endif
1162 if(truncate(rg_count_bytes)==new_limit)begin // if reached end of Flash memory
1163 let {x,y,z}<-change_phase.func(rg_phase,rg_count_bits,smf&cr_apms);
1164 rg_phase<=z;
1165 if(z==DataRead_phase)
1166 read_true <= True;
1167 sr_tcf<=y; // set completion of transfer flag
1168 rg_count_bytes<=0;
1169 rg_count_bits<=0;
1170 end
1171 else begin
1172 rg_count_bytes<=count_byte;
1173 rg_count_bits<=count_bits;
1174 end
1175 end
1176 else begin // keep looping untill abort signal is not raised.
1177 rg_count_bytes<=count_byte;
1178 rg_count_bits<=count_bits;
1179 end
1180 dr<=data_reg;
1181 sr_smf<=smf;
1182 end
1183 endrule
1184
1185 /* write data from the FIFO to the FLASH. Simulataneously*/
1186 (*descending_urgency="rl_data_write_phase,rl_read_request_from_AXI"*)
1187 (*descending_urgency="rl_data_write_phase,rl_write_request_from_AXI"*)
1188 rule rl_data_write_phase(rg_phase==DataWrite_phase && transfer_cond && clock_cond && !qspi_flush);
1189 if(half_cycle_delay)
1190 half_cycle_delay<=False;
1191 else begin
1192 Bit#(8) data_reg=fifo.first()[0];
1193 Bit#(32) count_byte=rg_count_bytes;
1194 Bit#(32) count_bits=rg_count_bits;
1195 Bit#(4) enable_o=0;
1196 /* write incoming bit to the data register */
1197 if(ccr_dmode==1)begin // single line mode;
1198 enable_o=4'b1101;
1199 rg_output<={1'b1,1'b0,1'b0,data_reg[rg_count_bits-1]};
1200 count_bits=count_bits-1;
1201 end
1202 else if(ccr_dmode==2)begin // dual line mode;
1203 enable_o=4'b1111;
1204 rg_output<={1'b1,1'b0,data_reg[rg_count_bits-1:rg_count_bits-2]};
1205 count_bits=count_bits-2;
1206 end
1207 else if(ccr_dmode==3) begin// quad line mode;
1208 enable_o=4'b1111;
1209 rg_output<=data_reg[rg_count_bits-1:rg_count_bits-4];
1210 count_bits=count_bits-4;
1211 end
1212 `ifdef verbose1 $display("Executing DataWrite Phase SPI Mode: %b DLR : %d Count_bits: %d Input :%b Enable: %b",ccr_dmode,dlr,rg_count_bits,rg_input,enable_o); `endif
1213
1214 /* write the last successfully received byte into the FIFO */
1215 if(ccr_dmode==1)begin// single line mode
1216 if(rg_count_bits==1)begin // multiple of eight bits have been read.
1217 fifo.deq(1);
1218 count_byte=count_byte+1;
1219 count_bits=8;
1220 end
1221 end
1222 else if(ccr_dmode==2) begin // dual line mode
1223 if(rg_count_bits==2)begin // multiple of eight bits have been read.
1224 fifo.deq(1);
1225 count_byte=count_byte+1;
1226 count_bits=8;
1227 end
1228 end
1229 else if(ccr_dmode==3) begin // quad line mode
1230 if(rg_count_bits==4)begin // multiple of eight bits have been read.
1231 fifo.deq(1);
1232 count_byte=count_byte+1;
1233 count_bits=8;
1234 end
1235 end
1236
1237 /* condition for termination of dataread_phase */
1238 if(dlr!='hFFFFFFFF)begin // if limit is not undefined
1239 if(rg_count_bytes==dlr)begin // if limit has bee reached.
1240 rg_phase<=Idle;
1241 sr_tcf<=1; // set completion of transfer flag
1242 rg_count_bytes<=0;
1243 rg_count_bits<=0;
1244 end
1245 else begin
1246 rg_count_bytes<=count_byte;
1247 rg_count_bits<=count_bits;
1248 end
1249 end
1250 else if(dcr_fsize!='h1f)begin // if limit is not infinite
1251 Bit#(32) new_limit=1<<(dcr_fsize);
1252 if(truncate(rg_count_bytes)==new_limit)begin // if reached end of Flash memory
1253 rg_phase<=Idle;
1254 sr_tcf<=1; // set completion of transfer flag
1255 rg_count_bytes<=0;
1256 rg_count_bits<=0;
1257 end
1258 else begin
1259 rg_count_bytes<=count_byte;
1260 rg_count_bits<=count_bits;
1261 end
1262 end
1263 else begin // keep looping untill abort signal is not raised.
1264 rg_count_bytes<=count_byte;
1265 rg_count_bits<=count_bits;
1266 end
1267 rg_output_en<=enable_o;
1268 end
1269 endrule
1270
1271 rule display_all_Registers;
1272 `ifdef verbose1 $display($time,"\tPhase: ",fshow(rg_phase)," CR WRitten %d",wr_instruction_written, "Address Written: %d",wr_address_written); `endif
1273 `ifdef verbose1 $display($time,"\tCR: %h\tDCR: %h\tSR: %h\tFCR: %h",cr,dcr,sr,fcr); `endif
1274 `ifdef verbose1 $display($time,"\tDLR: %h\tCCR: %h\tAR: %h\tABR: %h",dlr,ccr,ar,abr); `endif
1275 `ifdef verbose1 $display($time,"\tDR: %h\tPSMKR: %h\tPSMAR: %h\tPIR: %h",dr,psmkr,psmar,pir,"\n"); `endif
1276 endrule
1277
1278 `ifdef simulate
1279 rule delay_phase(((wr_sdr_clock && ccr_ddrm==0) || (ddr_clock && ccr_ddrm==1)));
1280 rg_phase_delayed<=rg_phase;
1281 endrule
1282 `endif
1283
1284 interface QSPI_out out;
1285 method bit clk_o;
1286 return delay_ncs==1?dcr_ckmode:rg_clk;
1287 endmethod
1288 method Bit#(9) io0_sdio_ctrl;
1289 return sdio0r[8:0];
1290 endmethod
1291 method Bit#(9) io1_sdio_ctrl;
1292 return sdio1r[8:0];
1293 endmethod
1294 method Bit#(9) io2_sdio_ctrl;
1295 return sdio2r[8:0];
1296 endmethod
1297 method Bit#(9) io3_sdio_ctrl;
1298 return sdio3r[8:0];
1299 endmethod
1300 method Bit#(4) io_o;
1301 return rg_output;
1302 endmethod
1303 method Bit#(4) io_enable;
1304 return rg_output_en;
1305 endmethod
1306 method Action io_i (Bit#(4) io_in); // in
1307 rg_input<=io_in;
1308 endmethod
1309 method bit ncs_o = ncs;
1310 endinterface
1311
1312 interface slave= s_xactor.axi_side;
1313
1314 method Bit#(6) interrupts; // 0=TOF, 1=SMF, 2=Threshold, 3=TCF, 4=TEF 5=request_ready
1315 return {pack(rg_request_ready),sr_tef&cr_teie, sr_tcf&cr_tcie, sr_ftf&cr_ftie, sr_smf&cr_smie , sr_tof&cr_toie};
1316 endmethod
1317 `ifdef simulate method curphase = rg_phase_delayed; `endif
1318 endmodule
1319
1320 endpackage
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