projects / shakti-peripherals.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
convert qspi to get/put
[shakti-peripherals.git] / src / peripherals / qspi / qspi.bsv
1 /*
2 Copyright (c) 2013, IIT Madras
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
6
7 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
8 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
9 * Neither the name of IIT Madras nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
10
11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
13 */
14 package qspi;
15 /*
16 TODOs
17 To use the following registers:
18 dcr_csht
19 * Done Pre-scaler.
20 > Memory mapped mode should continue to fetch data and fill the fifo even if the Core
21 is not requesting
22 * Done Status polling mode.
23 > This could not be replicated since the tof flag is set.
24 Memory mapped mode with dcyc =10 creates an extra cycle after Dummy phase.
25 > Data Read phase is on posedge and Data write is on negdege
26 -- send the received arid and bid's so that DMA can identify. duplicate instead of extend
27 */
28 import TriState::*;
29 import ConcatReg ::*;
30 import Semi_FIFOF :: *;
31 import AXI4_Lite_Types :: *;
32 import AXI4_Lite_Fabric :: *;
33 import FIFO::*;
34 import FIFOF::*;
35 import SpecialFIFOs::*;
36 import MIMO::*;
37 import DefaultValue :: *;
38 `include "instance_defines.bsv"
39 `include "qspi.defs"
40 import ConfigReg::*;
41 import Vector::*;
42 import UniqueWrappers :: * ;
43 import DReg::*;
44 import BUtils::*;
45 (*always_ready, always_enabled*)
46 interface QSPI_out;
47 /*(* always_ready, result="clk_o" *) */
48 interface Get#(Bit#(1)) clk_o;
49 /*(* always_ready, result="io_o" *) */
50 interface Get#(Bit#(4)) io_out;
51 /*(* always_ready, result="io0_sdio_ctrl" *) */
52 method Bit#(9) io0_sdio_ctrl;
53 /*(* always_ready, result="io1_sdio_ctrl" *) */
54 method Bit#(9) io1_sdio_ctrl;
55 /*(* always_ready, result="io2_sdio_ctrl" *) */
56 method Bit#(9) io2_sdio_ctrl;
57 /*(* always_ready, result="io3_sdio_ctrl" *) */
58 method Bit#(9) io3_sdio_ctrl;
59 /*(* always_ready, result="io_enable" *)*/
60 interface Get#(Bit#(4)) io_outen;
61 /*(* always_ready, always_enabled *) */
62 //method Action io_i ((* port="io_i" *) Bit#(4) io_in); // in
63 interface Put#(Bit#(4)) io_in;
64 /*(* always_ready, result="ncs_o" *) */
65 interface Get#(Bit#(1)) ncs_o;
66 endinterface
67
68 interface Ifc_qspi;
69 interface QSPI_out out;
70 interface AXI4_Lite_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) slave;
71 method Bit#(6) interrupts; // 0=TOF, 1=SMF, 2=Threshold, 3=TCF, 4=TEF 5 = request_ready
72 `ifdef simulate
73 method Phase curphase;
74 `endif
75 endinterface
76
77 function Reg#(t) readOnlyReg(t r);
78 return (interface Reg;
79 method t _read = r;
80 method Action _write(t x) = noAction;
81 endinterface);
82 endfunction
83
84 function Reg#(t) conditionalWrite(Reg#(t) r, Bool a);
85 return (interface Reg;
86 method t _read = r._read;
87 method Action _write(t x);
88 if(a)
89 r._write(x);
90 endmethod
91 endinterface);
92 endfunction
93
94 function Reg#(t) clearSideEffect(Reg#(t) r, Action a, Action b)
95 provisos( Literal#(t),Eq#(t));
96 return (interface Reg;
97 method t _read = r._read;
98 method Action _write(t x);
99 r._write(x);
100 if(x==1) begin
101 a;
102 b;
103 end
104 endmethod
105 endinterface);
106 endfunction
107
108 function Reg#(Bit#(32)) writeSideEffect(Reg#(Bit#(32)) r, Action a);
109 return (interface Reg;
110 method Bit#(32) _read = r._read;
111 method Action _write(Bit#(32) x);
112 r._write(x);
113 a;
114 endmethod
115 endinterface);
116 endfunction
117
118 function Reg#(Bit#(n)) writeCCREffect(Reg#(Bit#(n)) r, Action a, Action b);
119 return (interface Reg;
120 method Bit#(n) _read = r._read;
121 method Action _write(Bit#(n) x);
122 r._write(x);
123 `ifdef verbose1 $display("x: %h",x); `endif
124 if(x[11:10]==0 && (x[27:26] == 'b00 || x[27:26]=='b01 || x[25:24]=='b0) && x[9:8]!=0) begin // no address required and nodata from firmware (i.e. no write)
125 a;
126 end
127 if(x[27:26]=='b11) //Memory Mapped Mode
128 b;
129 endmethod
130 endinterface);
131 endfunction
132
133 typedef enum {Instruction_phase=0,
134 Address_phase=1,
135 AlternateByte_phase=2,
136 Dummy_phase=3,
137 DataRead_phase=4,
138 DataWrite_phase=5,
139 Idle=6} Phase deriving (Bits,Eq,FShow);
140
141 (*synthesize*)
142 module mkqspi(Ifc_qspi);
143
144 AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE) s_xactor <- mkAXI4_Lite_Slave_Xactor;
145 /*************** List of implementation defined Registers *****************/
146 Reg#(bit) rg_clk <-mkReg(1);
147 Reg#(Bit#(8)) rg_clk_counter<-mkReg(0);
148 MIMOConfiguration cfg=defaultValue;
149 cfg.unguarded=True;
150 MIMO#(4,4,16,Bit#(8)) fifo <-mkMIMO(cfg);
151 Reg#(Phase) rg_phase <-mkReg(Idle);
152 Reg#(Phase) rg_phase_delayed <-mkReg(Idle);
153 Reg#(Bit#(4)) rg_output <-mkReg(0);
154 Reg#(Bit#(4)) rg_output_en <-mkReg(0);
155 Reg#(Bool) rg_input_en <-mkReg(False);
156 Wire#(Bit#(4)) rg_input <-mkDWire(0);
157 Reg#(Bit#(32)) rg_count_bits <-mkReg(0); // count bits to be transfered
158 Reg#(Bit#(32)) rg_count_bytes <-mkReg(0); // count bytes to be transfered
159 Wire#(Bool) wr_sdr_clock <-mkDWire(False); // use this to trigger posedge of sclk
160 Reg#(Bool) wr_sdr_delayed <- mkReg(False);
161 Reg#(Bool) wr_instruction_written<-mkDReg(False); // this wire is se when the instruction is written by the AXI Master
162 Reg#(Bool) wr_address_written<-mkDReg(False); // this wire is set when the address is written by the AXI Master
163 Reg#(Bool) wr_read_request_from_AXI<-mkDReg(False); // this wire is set when the address is written by the AXI Master
164 Reg#(Bool) wr_data_written<-mkDReg(False); // this wire is set when the data is written by the AXI Master
165 Reg#(Bool) instruction_sent<-mkReg(False); // This register is set when the instruction has been sent once to the flash
166 Reg#(Bit#(1)) ncs <-mkReg(1); // this is the chip select
167 Reg#(Bit#(1)) delay_ncs <-mkReg(1); // this is the chip select
168 Wire#(Bool) wr_status_read<-mkDWire(False); // this wire is set when the status register is written
169 Wire#(Bool) wr_data_read<-mkDWire(False); // this wire is set when the data register is written
170 Reg#(Bool) half_cycle_delay<-mkReg(False);
171 Reg#(Bit#(16)) timecounter<-mkReg(0);
172 Reg#(Bool) read_true <- mkReg(False);
173 Reg#(Bool) first_read <- mkReg(False);
174 /*************** End of implementation defined Registers *****************/
175
176 /*************** List of QSPI defined Registers *****************/
177 Reg#(Bit#(1)) sr_busy <-mkConfigReg(0); // set when the operation is in progress.
178 Reg#(Bit#(5)) sr_flevel <-mkReg(0); // FIFO Level. Number of valid bytes held in the FIFO. 0: empty
179 Reg#(Bit#(1)) sr_tof <-mkReg(0); // set when the timeout occurs.
180 Reg#(Bit#(1)) sr_smf <-mkReg(0); // set when the unmasked receieved data matches psmar.
181 Reg#(Bit#(1)) sr_ftf <-mkReg(0); // set when the FIFO threshold is reached.
182 Reg#(Bit#(1)) sr_tcf <-mkReg(0); // set when programmed number of data has been transfered or when aborted.
183 Reg#(Bit#(1)) delay_sr_tcf <-mkReg(0); // set when programmed number of data has been transfered or when aborted.
184 Reg#(Bit#(1)) sr_tef <-mkReg(0); // set when an error occurs on transfer.
185 Reg#(Bit#(32)) sr = concatReg9(readOnlyReg(19'd0),readOnlyReg(sr_flevel),readOnlyReg(2'd0),readOnlyReg(sr_busy),readOnlyReg(sr_tof),readOnlyReg(sr_smf),readOnlyReg(sr_ftf),readOnlyReg(sr_tcf),readOnlyReg(sr_tef));
186
187
188 Reg#(Bit#(8)) prescaler<-mkReg(0);
189 Reg#(Bit#(8)) cr_prescaler=conditionalWrite(prescaler,sr_busy==0); // prescaler register part of the control register.
190 Reg#(Bit#(1)) pmm <-mkReg(0);
191 Reg#(Bit#(1)) cr_pmm =conditionalWrite(pmm,sr_busy==0); // polling match mode. 0: AND match and 1: OR match.
192 Reg#(Bit#(1)) apms <-mkReg(0);
193 Reg#(Bit#(1)) cr_apms =conditionalWrite(apms,sr_busy==0); // automatic poll mode stop. 1: stop when match. 0: stopped by disabling qspi.
194 Reg#(Bit#(1)) cr_toie <-mkReg(0); // enabled interrupt on time-out.
195 Reg#(Bit#(1)) cr_smie <-mkReg(0); // enables status match interrupt.
196 Reg#(Bit#(1)) cr_ftie <-mkReg(0); // enables interrupt on FIFO threshold.
197 Reg#(Bit#(1)) cr_tcie <-mkReg(0); // enables interrupt on completion of transfer.
198 Reg#(Bit#(1)) cr_teie <-mkReg(0); // enables interrupt on error of transfer.
199 Reg#(Bit#(4)) cr_fthres<-mkReg(0); // defines the number of bytes in the FIFO that will cause the FTF in sr to be raised.
200 Reg#(Bit#(1)) fsel<-mkReg(0);
201 Reg#(Bit#(1)) cr_fsel=conditionalWrite(fsel,sr_busy==0); // used for flash memory selection TODO: Not required.
202 Reg#(Bit#(1)) dfm<-mkReg(0);
203 Reg#(Bit#(1)) cr_dfm =conditionalWrite(dfm,sr_busy==0); // used for dual flash mode TODO: Not required.
204 Reg#(Bit#(1)) sshift<-mkReg(0);
205 Reg#(Bit#(1)) cr_sshift =conditionalWrite(sshift,sr_busy==0); // sample shift to account for delays from the flash. TODO: Might not be required.
206 Reg#(Bit#(1)) tcen<-mkReg(0);
207 Reg#(Bit#(1)) cr_tcen =conditionalWrite(tcen,sr_busy==0); // enables the timeout counter.
208 Reg#(Bit#(1)) cr_dmaen <- mkReg(0); // enables the dma transfer.
209 Reg#(Bit#(1)) cr_abort <- mkReg(0); // this bit aborts the ongoing transaction.
210 Reg#(Bit#(1)) cr_en <-mkReg(0); // this bit enables the qspi.
211 Reg#(Bit#(32)) cr=concatReg19(cr_prescaler,cr_pmm,cr_apms,readOnlyReg(1'b0),cr_toie,cr_smie,cr_ftie,cr_tcie,cr_teie,readOnlyReg(4'd0),cr_fthres,cr_fsel,cr_dfm,readOnlyReg(1'b0),cr_sshift,cr_tcen,cr_dmaen,cr_abort,cr_en);
212
213 Reg#(Bit#(5)) fsize<-mkReg(0);
214 Reg#(Bit#(5)) dcr_fsize =conditionalWrite(fsize,sr_busy==0); // flash memory size.
215 Reg#(Bit#(3)) csht <-mkReg(0);
216 Reg#(Bit#(3)) dcr_csht = conditionalWrite(csht,sr_busy==0); // chip select high time.
217 Reg#(Bit#(1)) ckmode <-mkReg(0);
218 Reg#(Bit#(1)) dcr_ckmode =conditionalWrite(ckmode,sr_busy==0); // mode 0 or mode 3.
219 Reg#(Bit#(8)) dcr_mode_byte <- mkReg(0);
220 Reg#(Bit#(32)) dcr = concatReg7(readOnlyReg(3'd0),dcr_mode_byte,dcr_fsize,readOnlyReg(5'd0),dcr_csht,readOnlyReg(7'd0),dcr_ckmode);
221 Reg#(Bit#(32)) rg_mode_bytes = concatReg2(dcr_mode_byte,readOnlyReg(24'd0));
222 Reg#(Bit#(5)) rg_mode_byte_counter <- mkReg('d31);
223
224 Reg#(Bit#(1)) fcr_ctof <-mkReg(0); // writing 1 clears the sr_tof flag.
225 Reg#(Bit#(1)) fcr_csmf <-mkReg(0); // writing 1 clears the sr_smf flag.
226 Reg#(Bit#(1)) fcr_ctcf <-mkReg(0); // writing 1 clears the sr_tcf flag.
227 Reg#(Bit#(1)) fcr_ctef <-mkReg(0); // writing 1 clears the sr_tef flag.
228 Reg#(Bit#(32)) fcr=concatReg6(readOnlyReg(27'd0),clearSideEffect(fcr_ctof,sr_tof._write(0),noAction),clearSideEffect(fcr_csmf,sr_smf._write(0),noAction),readOnlyReg(1'b0),clearSideEffect(fcr_ctcf,sr_tcf._write(0),delay_sr_tcf._write(0)),clearSideEffect(fcr_ctef,sr_tef._write(0),noAction));
229
230 Reg#(Bit#(32)) data_length<-mkReg(0);
231 Reg#(Bit#(32)) dlr=conditionalWrite(data_length,sr_busy==0); // data length register
232
233 Reg#(Bit#(1)) ddrm<-mkReg(0);
234 Reg#(Bit#(1)) ccr_ddrm =conditionalWrite(ddrm,sr_busy==0); // double data rate mode.
235 Reg#(Bit#(1)) dhhc <-mkReg(0);
236 Reg#(Bit#(1)) ccr_dhhc =conditionalWrite(dhhc,sr_busy==0); // delay output by 1/4 in DDR mode. TODO: Not required.
237 Reg#(Bit#(1)) sioo <-mkReg(0);
238 Reg#(Bit#(1)) ccr_sioo =conditionalWrite(sioo,sr_busy==0); // send instruction based on mode selected.
239 Reg#(Bit#(2)) fmode <-mkReg(0);
240 Reg#(Bit#(2)) ccr_fmode =conditionalWrite(fmode,sr_busy==0); // 00: indirect Read, 01: indirect Write, 10: Auto polling, 11: MMapped.
241 Reg#(Bit#(2)) dmode <-mkReg(0);
242 Reg#(Bit#(2)) ccr_dmode =conditionalWrite(dmode,sr_busy==0); // data mode. 01: single line, 10: two line, 11: four lines.
243 Reg#(Bit#(5)) dcyc <-mkReg(0);
244 Reg#(Bit#(5)) ccr_dcyc =conditionalWrite(dcyc,sr_busy==0); // number of dummy cycles.
245 Reg#(Bit#(2)) absize <-mkReg(0);
246 Reg#(Bit#(2)) ccr_absize=conditionalWrite(absize,sr_busy==0); // number of alternate byte sizes.
247 Reg#(Bit#(2)) abmode <-mkReg(0);
248 Reg#(Bit#(2)) ccr_abmode=conditionalWrite(abmode,sr_busy==0); // alternate byte mode.
249 Reg#(Bit#(2)) adsize <-mkReg(0);
250 Reg#(Bit#(2)) ccr_adsize=conditionalWrite(adsize,sr_busy==0); // address size.
251 Reg#(Bit#(2)) admode <-mkReg(0);
252 Reg#(Bit#(2)) ccr_admode=conditionalWrite(admode,sr_busy==0); // address mode.
253 Reg#(Bit#(2)) imode <-mkReg(0);
254 Reg#(Bit#(2)) ccr_imode =conditionalWrite(imode,sr_busy==0); // instruction mode.
255 Reg#(Bit#(8)) instruction <-mkReg(0);
256 Reg#(Bit#(8)) ccr_instruction =conditionalWrite(instruction,sr_busy==0); // instruction to be sent externally.
257 Reg#(Bit#(1)) ccr_dummy_confirmation <- mkReg(0); //Programming Dummy confirmation bit needed by Micron model to trigger XIP mode
258 Reg#(Bit#(1)) ccr_dummy_bit <- mkReg(0); //Dummy bit to be sent
259 Reg#(Bit#(32)) ccr =writeCCREffect(concatReg14(ccr_ddrm,ccr_dhhc,ccr_dummy_bit,ccr_sioo,ccr_fmode,ccr_dmode,ccr_dummy_confirmation,ccr_dcyc,ccr_absize,ccr_abmode,ccr_adsize,ccr_admode,ccr_imode,ccr_instruction),wr_instruction_written._write(True),first_read._write(True));
260
261 Reg#(Bit#(32)) mm_data_length <-mkConfigReg(0);
262 Reg#(Bit#(28)) mm_address <-mkConfigReg(0);
263 Reg#(Bit#(28)) rg_prev_addr <- mkConfigReg(0);
264 Reg#(Bit#(32)) rg_address <-mkReg(0);
265 Reg#(Bit#(32)) ar =conditionalWrite(writeSideEffect(rg_address,wr_address_written._write(True)),sr_busy==0 && ccr_fmode!='b11); // address register
266
267 Reg#(Bit#(32)) rg_alternatebyte_reg<-mkReg(0);
268 Reg#(Bit#(32)) abr=conditionalWrite(rg_alternatebyte_reg,sr_busy==0); // alternate byte register
269
270 Reg#(Bit#(32)) rg_data <-mkReg(0);
271 Reg#(Bit#(32)) dr =writeSideEffect(rg_data,wr_data_written._write(True)); // data register
272
273 Reg#(Bit#(32)) rg_psmkr <-mkReg(0);
274 Reg#(Bit#(32)) psmkr =conditionalWrite(rg_psmkr,sr_busy==0); // polling status mask register
275
276 Reg#(Bit#(32)) rg_psmar <-mkReg(0);
277 Reg#(Bit#(32)) psmar =conditionalWrite(rg_psmar,sr_busy==0); // polling statue match register
278
279 Reg#(Bit#(16)) pir_interval <-mkReg(0); // polling interval
280 Reg#(Bit#(32)) pir =conditionalWrite(concatReg2(readOnlyReg(16'd0),pir_interval),sr_busy==0); // polling interval register
281
282 Reg#(Bit#(16)) lptr_timeout <-mkReg(0); // timeout period
283 Reg#(Bit#(32)) lptr =conditionalWrite(concatReg2(readOnlyReg(16'd0),lptr_timeout),sr_busy==0); // low power timeout register.
284 Reg#(Bool) thres <- mkReg(False);
285 Reg#(Bit#(32)) sdio0r <- mkReg(32'h00000073);
286 Reg#(Bit#(32)) sdio1r <- mkReg(32'h00000073);
287 Reg#(Bit#(32)) sdio2r <- mkReg(32'h00000073);
288 Reg#(Bit#(32)) sdio3r <- mkReg(32'h00000073);
289 Reg#(Bool) rg_request_ready <- mkReg(True);
290 Bool ddr_clock = ((wr_sdr_clock&&!wr_sdr_delayed)||(!wr_sdr_clock&&wr_sdr_delayed));
291 Bool transfer_cond = (sr_busy==1 && cr_abort==0 && cr_en==1);
292 Bool clock_cond = ((wr_sdr_clock && ccr_ddrm==0) || (ddr_clock && ccr_ddrm==1));
293 Bool qspi_flush = (cr_abort==1 || cr_en==0);
294 /*************** End of QSPI defined Registers *****************/
295 function Reg#(Bit#(32)) access_register(Bit#(8) address);
296 Reg#(Bit#(32)) register=(
297 case(address)
298 `CR : cr;
299 `DCR : dcr;
300 `FCR : fcr;
301 `DLR : dlr;
302 `CCR : ccr;
303 `AR : ar;
304 `ABR : abr;
305 `DR : dr;
306 `SR : sr;
307 `PSMKR : psmkr;
308 `PSMAR : psmar;
309 `PIR : pir;
310 `LPTR : lptr;
311 `SDIO0 : sdio0r;
312 `SDIO1 : sdio1r;
313 `SDIO2 : sdio2r;
314 `SDIO3 : sdio3r;
315 default: readOnlyReg(0);
316 endcase
317 );
318 return register;
319 endfunction
320
321 /* This function defines the next phase that needs to be executed. indicates if
322 the operation is over and also the value of rg_count_bits for the next phase*/
323 function Tuple3#(Bit#(32),Bit#(1),Phase) phase_change(Phase current_phase, Bit#(32) count_val, Bit#(1) smf);
324 Phase next_phase=Idle;
325 if(current_phase==Idle)
326 next_phase=Instruction_phase;
327 if(current_phase==Instruction_phase)
328 next_phase=Address_phase;
329 if(current_phase==Address_phase)
330 next_phase=AlternateByte_phase;
331 if(current_phase==AlternateByte_phase)
332 next_phase=Dummy_phase;
333 if(current_phase==Dummy_phase)
334 next_phase=(ccr_fmode=='b00)?DataWrite_phase:DataRead_phase;
335 if(current_phase==DataRead_phase)begin
336 if(ccr_fmode=='b01 || ccr_fmode=='b10) // indirect modes
337 next_phase=Idle;
338 else if(ccr_fmode=='b10) // auto-status polling mode
339 if(smf==1)
340 next_phase=Idle;
341 else
342 next_phase=Dummy_phase;
343 else
344 next_phase=DataRead_phase; //Memory Mapped mode
345 end
346 if(current_phase==DataWrite_phase)
347 next_phase=Idle;
348
349 if(next_phase==Instruction_phase && (ccr_imode==0||(ccr_sioo==1 && instruction_sent))) // if single instruction mode or no instruction mode
350 next_phase=Address_phase;
351 if(next_phase==Address_phase && ccr_admode==0)
352 next_phase=AlternateByte_phase;
353 if(next_phase==AlternateByte_phase && ccr_abmode==0)
354 next_phase=Dummy_phase;
355 if(next_phase==Dummy_phase && ccr_dcyc==0)
356 next_phase=ccr_fmode==0?DataWrite_phase:DataRead_phase;
357 if(next_phase==Dummy_phase && (ccr_fmode=='b10 && pir_interval==0))begin // TODO Check if this is correct or needs more logic.
358 next_phase=Instruction_phase;
359 end
360 if((next_phase==DataWrite_phase || next_phase==DataRead_phase) && ccr_dmode==0 && ccr_fmode!='b11)begin
361 if(ccr_fmode=='b01 || ccr_fmode=='b00)
362 next_phase=Idle;
363 else if(ccr_fmode=='b10)
364 if(smf==1)
365 next_phase=Idle;
366 else
367 next_phase=Dummy_phase;
368 end
369
370 if(next_phase==Instruction_phase)begin
371 count_val=8;
372 end
373 if(next_phase==Address_phase)begin
374 count_val=(ccr_fmode=='b11)?32:(case(ccr_adsize) 0:8; 1:16; 2:24; 3:32; endcase);
375 end
376 if(next_phase==AlternateByte_phase)begin
377 count_val=(case(ccr_absize) 0:8; 1:16; 2:24; 3:32; endcase);
378 end
379 if(next_phase==Dummy_phase)begin
380 count_val=(ccr_fmode=='b10)? zeroExtend(pir_interval):zeroExtend(ccr_dcyc);
381 end
382 if(next_phase==DataWrite_phase)begin
383 count_val=8;
384 end
385 if(next_phase==DataRead_phase)begin
386 count_val=0;
387 end
388 Bit#(1) tcf=0;
389 if(current_phase!=Idle && next_phase==Idle && (ccr_fmode=='b00 || ccr_fmode=='b01))begin // only in indirect mode raise completion of transfer TODO remove ccr_fmode=='b11 from this line.
390 tcf=1;
391 end
392 return tuple3(count_val,tcf,next_phase);
393 endfunction
394
395 Wrapper3#(Phase,Bit#(32),Bit#(1),Tuple3#(Bit#(32),Bit#(1),Phase)) change_phase<-mkUniqueWrapper3(phase_change);
396 /* This rule receives the write request from the AXI and updates the relevant
397 QSPI register set using the lower 12 bits as address map */
398 rule rl_write_request_from_AXI;
399 let aw <- pop_o (s_xactor.o_wr_addr);
400 let w <- pop_o (s_xactor.o_wr_data);
401 AXI4_Lite_Resp axi4_bresp = AXI4_LITE_OKAY;
402 if(ccr_fmode=='b11 && aw.awaddr[7:0]==`DR) begin //Undefined behavior when written into integral fields in CR, CCR!!!
403 axi4_bresp = AXI4_LITE_SLVERR;
404 `ifdef verbose $display("Sending AXI4_LITE_SLVERR because store in memory mapped mode and not clearing Interrupt Flags"); `endif
405 end
406 `ifdef verbose $display($time,"\tReceived AXI write request to Address: %h Data: %h Size: %h",aw.awaddr,w.wdata,aw.awsize); `endif
407 if(aw.awaddr[7:0]==`DR)begin
408 if(aw.awsize==0)begin
409 dr[7:0]<=w.wdata[7:0];
410 Vector#(4,Bit#(8)) temp=newVector();
411 temp[0]=w.wdata[7:0];
412 if(fifo.enqReadyN(1))
413 fifo.enq(1,temp);
414 end
415 else if(aw.awsize==1)begin
416 dr[15:0]<=w.wdata[15:0];
417 Vector#(4,Bit#(8)) temp = newVector();
418 temp[0]=w.wdata[7:0];
419 temp[1]=w.wdata[15:8];
420 if(fifo.enqReadyN(2))
421 fifo.enq(2,temp);
422 end
423 else if(aw.awsize==2)begin
424 dr<=w.wdata[31:0];
425 Vector#(4,Bit#(8)) temp = newVector();
426 temp[3]=w.wdata[31:24];
427 temp[2]=w.wdata[23:16];
428 temp[1]=w.wdata[15:8];
429 temp[0]=w.wdata[7:0];
430 if(fifo.enqReadyN(4))
431 fifo.enq(4,temp);
432 end
433 else begin
434 axi4_bresp = AXI4_LITE_SLVERR;
435 `ifdef verbose $display("Sending AXI4_LITE_SLVERR because DR awsize is 64-bit"); `endif
436 end
437 end
438 else begin
439 let reg1=access_register(aw.awaddr[7:0]);
440 `ifdef verbose $display("Write Reg access: %h Write Data: %h Size: %h",aw.awaddr[7:0],w.wdata,aw.awsize); `endif
441 //Byte and Half-Word Writes are not permitted in ConfigReg Space
442 if(aw.awsize==2) // 32 bits
443 reg1<=w.wdata[31:0];
444 else begin
445 axi4_bresp = AXI4_LITE_SLVERR;
446 `ifdef verbose $display("Sending SLVERR because Accessed register's awsize was different"); `endif
447 end
448 end
449
450 let b = AXI4_Lite_Wr_Resp {bresp: axi4_bresp, buser: aw.awuser};
451 s_xactor.i_wr_resp.enq (b);
452 endrule
453
454 /* This rule receives the read request from the AXI and responds with the relevant
455 QSPI register set using the lower 12 bits as address map */
456 (*descending_urgency="rl_read_request_from_AXI,rl_write_request_from_AXI"*) //experimental
457 rule rl_read_request_from_AXI(rg_request_ready==True);
458 let axir<- pop_o(s_xactor.o_rd_addr);
459 Bool request_ready = True;
460 `ifdef verbose $display($time,"\tReceived AXI read request to Address: %h Size: %h",axir.araddr,axir.arsize); `endif
461 if((axir.araddr[27:0]>=`STARTMM && axir.araddr[27:0]<=`ENDMM) && axir.araddr[31]==1'b1)begin // memory mapped space
462
463 wr_read_request_from_AXI<=True; //Could this lead to some error? Need to think about this, without fail
464 AXI4_Lite_Resp axi4_rresp = AXI4_LITE_OKAY;
465 mm_address<=truncate(axir.araddr);
466 Bit#(4) data_length = axir.arsize==0?1:axir.arsize==1?2:axir.arsize==2?4:8;
467 mm_data_length<= zeroExtend(data_length);
468 Bit#(28) address_limit = 1 << dcr_fsize;
469
470 //It is forbidden to access the flash bank area before the SPI is properly configured -- fmode is '11??
471 //If not sending a SLVERR now if the mode is not memory mapped and if an access is made outside allowed
472 if(ccr_fmode!='b11 || axir.araddr[27:0] > address_limit) begin
473 `ifdef verbose $display("Sending Slave Error ccr_fmode: %h mm_address: %h address_limit: %h dcr_fsize: %h",ccr_fmode,mm_address,address_limit, dcr_fsize); `endif
474 axi4_rresp = AXI4_LITE_SLVERR;
475 let r = AXI4_Lite_Rd_Data {rresp: axi4_rresp, rdata: 0 , ruser: 0};
476 s_xactor.i_rd_data.enq(r);
477 axi4_rresp = AXI4_LITE_SLVERR;
478 rg_phase <= Idle; //Will this work?
479 cr_en <= 0;
480 sr_busy <= 0;
481 ncs <= 1; //Just resetting all the parameters, just in case. Should Ask Neel
482 first_read <= True;
483 end
484 else if(sr_busy==1 ||thres) begin //Bus is busy with Memory mapped maybe?
485 `ifdef verbose $display($time,"sr_busy: %d, thres: %d rg_prev_addr: %h axir.araddr: %h fifo_count: %d", sr_busy, thres, rg_prev_addr, axir.araddr, fifo.count); `endif
486 Bit#(28) eff_addr = rg_prev_addr + zeroExtend(data_length);
487 if((eff_addr!= truncate(axir.araddr)) || pack(fifo.count)==0 || ccr_dummy_bit==1'b1) begin
488 `ifdef verbose $display($time,"Not Equal eff_addr: %h mm_address : %h axir.araddr: %h rg_prev_addr: %h data_length : %h sum : %h fifo.count: %h ccr_dummy_bit: %h",eff_addr,mm_address,axir.araddr,rg_prev_addr,data_length,rg_prev_addr+zeroExtend(data_length),pack(fifo.count),ccr_dummy_bit); `endif
489 sr_busy<=0;
490 rg_phase<=Idle;
491 ncs<=1;
492 fifo.clear();
493 thres <= False;
494 //$display($time,"Setting Thres to FALSE");
495 first_read <= True;
496 request_ready = False;
497 end
498 else if(!first_read) begin
499 request_ready = True;
500 rg_prev_addr <= truncate(axir.araddr);
501 Bit#(32) reg1 = 0;
502 if(axir.arsize==0) begin // 8 bits
503 if(fifo.deqReadyN(1))begin
504 let temp=fifo.first[0];
505 reg1=duplicate(temp);
506 fifo.deq(1);
507 end
508 end
509 else if(axir.arsize==1) begin // 16 bits
510 if(fifo.deqReadyN(2)) begin
511 let temp={fifo.first[0],fifo.first[1]};
512 reg1=duplicate(temp);
513 fifo.deq(2);
514 end
515 end
516 else if(axir.arsize==2) begin // 32 bits
517 if(fifo.deqReadyN(4)) begin
518 let temp={fifo.first[0],fifo.first[1],fifo.first[2],fifo.first[3]};
519 reg1=duplicate(temp);
520 fifo.deq(4);
521 end
522 end
523 else
524 axi4_rresp = AXI4_LITE_SLVERR;
525 `ifdef verbose $display("Sending Response to the core: reg1: %h", reg1); `endif
526 let r = AXI4_Lite_Rd_Data {rresp: axi4_rresp, rdata: duplicate(reg1) , ruser: 0};
527 s_xactor.i_rd_data.enq(r);
528 end
529 end
530 end
531 else begin
532 let reg1=access_register(axir.araddr[7:0]);
533 `ifdef verbose $display("Reg Read Access: %h arsize: %h",axir.araddr[7:0], axir.arsize); `endif
534 if(axir.araddr[7:0]==`SR)
535 wr_status_read<=True;
536 if(axir.araddr[7:0]==`DR)begin // accessing the data register for read.
537 `ifdef verbose $display("Accessed DR fifo_count : %d axi.arsize: %d", fifo.count, axir.arsize); `endif
538 if(ccr_fmode=='b10)
539 wr_data_read<=True;
540 if(axir.arsize==0) begin // 8 bits
541 if(fifo.deqReadyN(1))begin
542 let temp=fifo.first[0];
543 reg1=duplicate(temp);
544 fifo.deq(1);
545 end
546 end
547 else if(axir.arsize==1) begin // 16 bits
548 if(fifo.deqReadyN(2)) begin
549 let temp={fifo.first[0],fifo.first[1]};
550 reg1=duplicate(temp);
551 fifo.deq(2);
552 end
553 end
554 else /*if(axir.arsize==2)*/ begin // 32 bits -- Even if the request is a long int, respond with int since that's the max we can do
555 if(fifo.deqReadyN(4)) begin
556 let temp={fifo.first[0],fifo.first[1],fifo.first[2],fifo.first[3]};
557 reg1=duplicate(temp);
558 fifo.deq(4);
559 end
560 end
561 end
562 `ifdef verbose $display("Sending Response : reg1: %x", reg1); `endif
563 let r = AXI4_Lite_Rd_Data {rresp: AXI4_LITE_OKAY, rdata: duplicate(reg1) ,ruser: 0};
564 request_ready = True;
565 s_xactor.i_rd_data.enq(r);
566 end
567 rg_request_ready <= request_ready;
568 `ifdef verbose $display($time,"QSPI: Is Request ready? : %h",request_ready); `endif
569 endrule
570
571
572 rule timeout_counter;
573 if(cr_tcen==1 && sr_tof==0) // timecounter is enabled
574 if(timecounter==lptr_timeout[15:0])begin
575 timecounter<=0;
576 sr_tof<=1;
577 end
578 else
579 timecounter<=timecounter+1;
580 endrule
581
582 rule delayed_sr_tcf_signal(transfer_cond &&
583 ((ccr_ddrm==1 && ddr_clock && (ccr_admode!=0 || ccr_dmode!=0)) || wr_sdr_clock));
584 sr_tcf<=delay_sr_tcf;
585 endrule
586
587 rule delayed_ncs_generation;
588 delay_ncs<=ncs;
589 endrule
590
591 rule delay_sdr;
592 wr_sdr_delayed <= wr_sdr_clock;
593 endrule
594
595
596 /* This rule generates the clk signal. The Prescaler register defines the
597 division factor wrt to the Global clock. The prescaler will only work when the
598 chip select is low i.e when the operation has been initiated. */
599 rule rl_generate_clk_from_master;
600 if(delay_ncs==1)begin
601 rg_clk_counter<=0;
602 rg_clk<=dcr_ckmode;
603 `ifdef verbose1 $display("dcr_ckmode: %h",dcr_ckmode); `endif
604 end
605 else begin
606 let half_clock_value=cr_prescaler>>1;
607 if(cr_prescaler[0]==0)begin // odd division
608 if(rg_clk_counter<=half_clock_value)
609 rg_clk<=0;
610 else
611 rg_clk<=1;
612 if(rg_clk_counter==cr_prescaler)
613 rg_clk_counter<=0;
614 else
615 rg_clk_counter<=rg_clk_counter+1;
616 if(rg_clk_counter == half_clock_value || rg_clk_counter==cr_prescaler)begin
617 wr_sdr_clock<=rg_phase==DataRead_phase?unpack(~rg_clk):unpack(rg_clk);
618 end
619 end
620 else begin // even division
621 if(rg_clk_counter==half_clock_value)begin
622 rg_clk<=~rg_clk;
623 rg_clk_counter<=0;
624 wr_sdr_clock<=rg_phase==DataRead_phase?unpack(~rg_clk):unpack(rg_clk);
625 end
626 else if(delay_ncs==0)
627 rg_clk_counter<=rg_clk_counter+1;
628 end
629 end
630 endrule
631
632 /* update the status flag on each cycle */
633 rule rl_update_fifo_level;
634 sr_flevel<=pack(fifo.count);
635 endrule
636 /* set the fifo threshold flag when the FIFO level is equal to the FTHRESH value */
637 (*preempts="rl_set_busy_signal,rl_update_threshold_flag"*)
638 rule rl_update_threshold_flag;
639 if(ccr_fmode=='b00)begin// indirect write mode
640 sr_ftf<=pack(16-pack(fifo.count)>={1'b0,cr_fthres}+1);
641 end
642 else if(ccr_fmode=='b01) begin
643 sr_ftf<=pack(pack(fifo.count)>=({1'b0,cr_fthres}+1));
644 `ifdef verbose1 $display("fifo count: %d fthres: %d",fifo.count,cr_fthres); `endif
645 end
646 else if(ccr_fmode=='b10 && wr_status_read)begin // auto_status polling mode
647 sr_ftf<=1;
648 end
649 else if(ccr_fmode=='b10 && wr_data_read)begin // auto_status polling mode
650 sr_ftf<=0;
651 end
652 else if(ccr_fmode=='b11 && pack(fifo.count)>={1'b0,cr_fthres}+1) begin
653 ncs<=1;
654 sr_busy<=0;
655 rg_phase<=Idle; // Will this work?
656 thres<= True;
657 rg_request_ready <= True;
658 // $display($time,"THRES is being set to TRUE kyaaaa?");
659 end
660 endrule
661
662 /* If abort is raised or the QSPI is disabled go back to Idle Phase*/
663 //(*descending_urgency = "if_abort,rl_read_request_from_AXI"*)
664 //(*descending_urgency = "if_abort,rl_write_request_from_AXI"*)
665 (*preempts = "if_abort,rl_update_threshold_flag"*)
666 rule if_abort(qspi_flush);
667 //$display("Received Abort or Disable request, going to idle");
668 rg_phase<=Idle;
669 ncs <= 1;
670 sr_busy <= 0;
671 thres <= False;
672 read_true <= False;
673 first_read <= False;
674 instruction_sent <= False;
675 half_cycle_delay <= False;
676 fifo.clear(); //What if its already empty? clearing the fifo, so doesn't matter
677 endrule
678
679 /*operate the busy signal in different mode */
680 rule rl_reset_busy_signal(sr_busy==1);
681 if(cr_abort==1)begin
682 sr_busy<=0;
683 ncs<=1;
684 end
685 else if(ccr_fmode=='b00 || ccr_fmode=='b01)begin // indirect write or read mode;
686 if(/*fifo.count==0 &&*/ sr_tcf==1)begin // if FIFO is empty and the transaction is complete
687 sr_busy<=0;
688 ncs<=1;
689 end
690 end
691 else if(ccr_fmode=='b10)begin // automatic polling mode
692 if(sr_smf==1)begin
693 sr_busy<=0;
694 ncs<=1;
695 end
696 end
697 else if(ccr_fmode=='b11)begin
698 if(sr_tof==1 || cr_en==0 || cr_abort==1) begin// timeout event
699 sr_busy<=0;
700 ncs<=1;
701 end
702 end
703 endrule
704 (*descending_urgency="rl_set_busy_signal,rl_read_request_from_AXI"*)
705 (*descending_urgency="rl_set_busy_signal,rl_write_request_from_AXI"*)
706 rule rl_set_busy_signal(sr_busy==0 && rg_phase==Idle && cr_abort==0 && cr_en==1);
707 rg_output_en<=0;
708 instruction_sent<=False;
709 `ifdef verbose1 $display($time,"\tWaiting for change in phase wr_read_request_from_AXI: %b ccr_fmode: %h thres: %h",wr_read_request_from_AXI,ccr_fmode,thres); `endif
710 if(wr_instruction_written)begin
711 sr_busy<=1;
712 ncs<=0;
713 rg_phase<=Instruction_phase;
714 rg_count_bits<=8;
715 end
716 else if((wr_address_written && ccr_admode!=0 && (ccr_fmode=='b01 || ccr_dmode=='d0 || ccr_fmode=='b10))|| (wr_data_written && ccr_admode!=0 && ccr_dmode!=0 && ccr_fmode=='b00))begin
717 sr_busy<=1; // start some transaction
718 `ifdef verbose $display("Address Written and going to Some mode"); `endif
719 ncs<=0;
720 let {x,y,z}<-change_phase.func(rg_phase,0,0);
721 rg_count_bits<=x;
722 rg_count_bytes<=0;
723 rg_phase<=z;
724 `ifdef verbose $display("Mode is :",fshow(z),"Count_bits : %d",x); `endif
725 if(z==DataRead_phase)
726 read_true <= True;
727 end
728 else if(wr_read_request_from_AXI && ccr_fmode=='b11 && !thres)begin // memory-mapped mode.
729 `ifdef verbose $display("Entering Memory mapped mode"); `endif
730 sr_busy<=1;
731 ncs<=0;
732 let {x,y,z}<-change_phase.func(rg_phase,0,0);
733 rg_count_bits<=x;
734 rg_count_bytes<=0;
735 rg_phase<=z;
736 `ifdef verbose $display("rg_phase :",fshow(z)); `endif
737 if(z==DataRead_phase)
738 read_true <= True;
739 end
740 endrule
741
742 /* This rule generates the error signal interrupt in different scenarios */
743 rule set_error_signal;
744 Bit#(32) actual_address=1<<(dcr_fsize);
745 if(wr_address_written && ar>actual_address && (ccr_fmode=='b00 || ccr_fmode=='b01))
746 sr_tef<=1;
747 else if(wr_address_written && ar+dlr>actual_address &&(ccr_fmode=='b00 || ccr_fmode=='b01))
748 sr_tef<=1;
749 else if(wr_address_written)
750 sr_tef<=0;
751 endrule
752
753 /* Rule to transfer the instruction of 8-bits outside. THe size of instruction is fixed
754 to 8 bits by protocol. Instruction phase will always be in SDR mode */
755 rule rl_transfer_instruction(rg_phase==Instruction_phase && transfer_cond && wr_sdr_clock && !qspi_flush);
756 Bool end_of_phase=False;
757 let reverse_instruction=ccr_instruction;
758 let count_val=rg_count_bits;
759 `ifdef verbose1 $display("Executing Instruction Phase SPI Mode: %b Count_bits: %d InstructionReverse: %h",ccr_imode,rg_count_bits,reverse_instruction); `endif
760 Bit#(4) enable_o=0;
761 if(ccr_imode=='b01)begin // single spi mode;
762 enable_o=4'b1101;
763 rg_output<={1'b1,1'b0,1'b0,reverse_instruction[rg_count_bits-1]};
764 if(rg_count_bits==1)begin// end of instruction stream
765 end_of_phase=True;
766 end
767 else
768 count_val=rg_count_bits-1;
769 end
770 else if (ccr_imode=='b10)begin // dual mode;
771 enable_o=4'b1111;
772 rg_output<={1'b1,1'b0,reverse_instruction[rg_count_bits-1:rg_count_bits-2]};
773 if(rg_count_bits==2)begin// end of instruction stream
774 end_of_phase=True;
775 end
776 else
777 count_val=rg_count_bits-2;
778 end
779 else if (ccr_imode=='b11)begin // quad mode;
780 enable_o=4'b1111;
781 rg_output<=reverse_instruction[rg_count_bits-1:rg_count_bits-4];
782 if(rg_count_bits==4)begin// end of instruction stream
783 end_of_phase=True;
784 end
785 else
786 count_val=rg_count_bits-4;
787 end
788 if(end_of_phase || ccr_imode==0)begin // end of instruction or no instruction phase
789 let {x,y,z}<-change_phase.func(rg_phase,count_val,0);
790 instruction_sent<=True;
791 rg_count_bits<=x;
792 delay_sr_tcf<=y;
793 rg_phase<=z;
794 rg_count_bytes<=0;
795 if(ccr_ddrm==1)
796 half_cycle_delay<=True;
797 if(z==DataRead_phase)
798 read_true <= True;
799 end
800 else
801 rg_count_bits<=count_val;
802 rg_output_en<=enable_o;
803 endrule
804
805 /* Rule to transfer the address bits of address outside. The size of address is
806 defined by the ccr_adsize register in ccr */
807 rule rl_transfer_address(rg_phase==Address_phase && transfer_cond && clock_cond && !qspi_flush);
808 if(half_cycle_delay) begin
809 half_cycle_delay<=False;
810 read_true <= True; //A workaround for the delay .. For DDR mode, the clock should be pushed one cycle and not half
811 end
812 else if(read_true)
813 read_true <= False;
814 else begin
815 Bool end_of_phase=False;
816 Bit#(4) enable_o=0;
817 let count_val=rg_count_bits;
818 Bit#(32) address=(ccr_fmode=='b11)?zeroExtend(mm_address):ar;
819 rg_prev_addr <= truncate(address);
820 `ifdef verbose1 $display($time,"Executing Address Phase SPI Mode: %b Address Size: %d Count_bits: %d Address: %b",ccr_admode,ccr_adsize,rg_count_bits,address); `endif
821 if(ccr_admode=='b01)begin // single spi mode;
822 enable_o=4'b1101;
823 rg_output<={1'b1,1'b0,1'b0,address[rg_count_bits-1]};
824 `ifdef verbose $display($time,"Single: Sending Address bit %h bit_number: %d total_address: %h",rg_count_bits-1,address[rg_count_bits-1],address); `endif
825 if(rg_count_bits==1)begin// end of address stream
826 end_of_phase=True;
827 end
828 else
829 count_val=rg_count_bits-1;
830 end
831 else if (ccr_admode=='b10)begin // dual mode;
832 enable_o=4'b1111;
833 rg_output<={1'b1,1'b0,address[rg_count_bits-1:rg_count_bits-2]};
834 `ifdef verbose $display($time,"Double: Sending Address bit %h bit_number: %d total_address: %h",rg_count_bits-1,address[rg_count_bits-1],address); `endif
835 if(rg_count_bits==2)begin// end of address stream
836 end_of_phase=True;
837 end
838 else
839 count_val=rg_count_bits-2;
840 end
841 else if (ccr_admode=='b11)begin // quad mode;
842 enable_o=4'b1111;
843 rg_output<=address[rg_count_bits-1:rg_count_bits-4];
844 `ifdef verbose $display($time,"Quad: Sending Address bit %h bit_number: %d total_address: %h",rg_count_bits-1,address[rg_count_bits-1],address); `endif
845 if(rg_count_bits==4)begin// end of address stream
846 end_of_phase=True;
847 end
848 else
849 count_val=rg_count_bits-4;
850 end
851 if(end_of_phase || ccr_admode==0)begin // end of address phase
852 let {x,y,z}<-change_phase.func(rg_phase,count_val,0);
853 rg_count_bits<=x;
854 delay_sr_tcf<=y;
855 rg_phase<=z;
856 rg_count_bytes<=0;
857 if(z==DataRead_phase)
858 read_true <= True;
859 end
860 else
861 rg_count_bits<=count_val;
862 rg_output_en<=enable_o;
863 end
864 endrule
865
866 /* Rule to transfer the alternate bytes. The size of alternate bytes is
867 defined by the ccr_absize register in ccr */
868 rule rl_transfer_alternatebytes(rg_phase==AlternateByte_phase && transfer_cond && clock_cond && !qspi_flush);
869 Bool end_of_phase=False;
870 let count_val=rg_count_bits;
871 `ifdef verbose1 $display("Executing AltByte Phase SPI Mode: %b AltByte Size: %d Count_bits: %d AltByte: %b",ccr_abmode,ccr_absize,rg_count_bits,abr); `endif
872 Bit#(4) enable_o=0;
873 if(ccr_abmode=='b01)begin // single spi mode;
874 enable_o=4'b1101;
875 rg_output<={1'b1,1'b0,1'b0,abr[rg_count_bits-1]};
876 if(rg_count_bits==1)begin// end of instruction stream
877 end_of_phase=True;
878 end
879 else
880 count_val=rg_count_bits-1;
881 end
882 else if (ccr_abmode=='b10)begin // dual mode;
883 enable_o=4'b1111;
884 rg_output<={1'b1,1'b0,abr[rg_count_bits-1:rg_count_bits-2]};
885 if(rg_count_bits==2)begin// end of instruction stream
886 end_of_phase=True;
887 end
888 else
889 count_val=rg_count_bits-2;
890 end
891 else if (ccr_abmode=='b11)begin // quad mode;
892 enable_o=4'b1111;
893 rg_output<=abr[rg_count_bits-1:rg_count_bits-4];
894 if(rg_count_bits==4)begin// end of instruction stream
895 end_of_phase=True;
896 end
897 else
898 count_val=rg_count_bits-4;
899 end
900 if(end_of_phase || ccr_abmode==0)begin // end of alternate byte phase
901 let {x,y,z}<-change_phase.func(rg_phase,count_val,0);
902 rg_count_bits<=x;
903 delay_sr_tcf<=y;
904 rg_phase<=z;
905 rg_count_bytes<=0;
906 if(z==DataRead_phase)
907 read_true <= True;end
908 else
909 rg_count_bits<=count_val;
910 rg_output_en<=enable_o;
911 endrule
912
913
914 rule rl_transfer_dummy_cycle(rg_phase==Dummy_phase && transfer_cond && wr_sdr_clock && !qspi_flush);
915 let {x,y,z} <- change_phase.func(rg_phase,rg_count_bits,0);
916 Bit#(5) count_val = rg_mode_byte_counter;
917 Bit#(4) enable_o = rg_output_en;
918 `ifdef verbose $display("\t Executing Dummy Phase: rg_mode_bytes: %b rg_mode_byte_counter: %d",rg_mode_bytes, rg_mode_byte_counter); `endif
919 if(ccr_dmode==1) begin
920 if(ccr_dummy_confirmation==1) begin
921 //rg_output_en <= 4'b1101;
922 enable_o = 4'b1101;
923 rg_output <= {1'b1,1'b0,1'b0,rg_mode_bytes[rg_mode_byte_counter]};
924 if(count_val!=0)
925 count_val = count_val - 1;
926 else
927 enable_o = 4'b0000;
928 end
929 else begin
930 //rg_output_en <= 4'b1101;
931 enable_o = 4'b1101;
932 rg_output <= {1'b1,1'b0,1'b0,1'b0};
933 end
934 end
935 else if(ccr_dmode==2) begin
936 if(ccr_dummy_confirmation==1) begin
937 //rg_output_en <= 4'b1111;
938 enable_o = 4'b1111;
939 rg_output <= {1'b1,1'b0,rg_mode_bytes[rg_mode_byte_counter:rg_mode_byte_counter-1]};
940 if(count_val!=0)
941 count_val = count_val - 2;
942 else
943 enable_o = 4'b0000;
944 end
945 else begin
946 //rg_output_en <= 4'b1100;
947 enable_o = 4'b1100;
948 rg_output <= {1'b1,1'b0,1'b0,1'b0};
949 end
950 end
951 else begin
952 if(ccr_dummy_confirmation==1) begin
953 //rg_output_en <= 4'b1111;
954 enable_o = 4'b1111;
955 rg_output <= rg_mode_bytes[rg_mode_byte_counter:rg_mode_byte_counter-3];
956 if(count_val!=3)
957 count_val = count_val - 4;
958 else
959 enable_o = 4'b0000;
960 end
961 else begin
962 //rg_output_en <= 4'b0000;
963 enable_o = 4'b0000;
964 end
965 end
966 if(rg_count_bits==0 || (rg_count_bits==1 && z!=DataRead_phase))begin // end of dummy cycles;
967 delay_sr_tcf<=y;
968 rg_phase<=z;
969 `ifdef verbose $display("From Dummy to :",fshow(z)); `endif
970 if(z==DataRead_phase)
971 read_true <= True;
972 rg_count_bytes<=0;
973 rg_count_bits<=x;
974 rg_mode_byte_counter <= 'd-1; //All ones
975 if(ccr_ddrm==1)
976 half_cycle_delay<=True;
977 end
978 else begin
979 rg_count_bits<=rg_count_bits-1;
980 rg_mode_byte_counter <= count_val;
981 rg_output_en <= enable_o;
982 end
983 endrule
984
985
986 /* Rule to transfer the dummy_cycles. The size of dummy cycles is
987 defined by the ccr_dcyc register in ccr. The number of dummy cycles should be calculated of
988 the complete cycle even in DDR mode hence using sdr clock*/
989 /* rule rl_transfer_dummy_cycle(rg_phase==Dummy_phase && transfer_cond && wr_sdr_clock && !qspi_flush);
990 let {x,y,z}<-change_phase.func(rg_phase,rg_count_bits,0);
991 `ifdef verbose $display($time,"Executing Dummy Phase, Dummy_confirmation_bit : %d dummy_bit : %d", ccr_dummy_confirmation, ccr_dummy_bit); `endif
992 if(ccr_dmode==1) begin
993 if(ccr_dummy_confirmation==1) begin
994 rg_output_en <= 4'b1101;
995 rg_output <= {1'b1,1'b0,1'b0,ccr_dummy_bit};
996 ccr_dummy_confirmation<=0;
997 end
998 else begin
999 rg_output_en <= 4'b1101;
1000 rg_output <= {1'b1,1'b0,1'b0,1'b0};
1001 end
1002 end
1003 else if(ccr_dmode==2) begin
1004 if(ccr_dummy_confirmation==1) begin
1005 rg_output_en <= 4'b1101;
1006 rg_output <= {1'b1,1'b0,1'b0,ccr_dummy_bit};
1007 ccr_dummy_confirmation <= 0;
1008 end
1009 else begin
1010 rg_output_en <= 4'b1100;
1011 rg_output <= {1'b1,1'b0,1'b0,1'b0};
1012 end
1013 end
1014 else begin
1015 if(ccr_dummy_confirmation==1) begin
1016 `ifdef verbose $display("Data going to output %d", ccr_dummy_bit); `endif
1017 rg_output_en <= 1;
1018 rg_output[0] <= ccr_dummy_bit;
1019 ccr_dummy_confirmation<=0;
1020 end
1021 else
1022 rg_output_en <= 0;
1023 end
1024 if(rg_count_bits==0 || (rg_count_bits==1 && z!=DataRead_phase))begin // end of dummy cycles;
1025 delay_sr_tcf<=y;
1026 rg_phase<=z;
1027 `ifdef verbose $display("From Dummy to :",fshow(z)); `endif
1028 if(z==DataRead_phase)
1029 read_true <= True;
1030 rg_count_bytes<=0;
1031 rg_count_bits<=x;
1032 if(ccr_ddrm==1)
1033 half_cycle_delay<=True;
1034 end
1035 else begin
1036 rg_count_bits<=rg_count_bits-1;
1037 end
1038 endrule*/
1039
1040 /* read data from the flash memory and store it in the DLR register. Simulataneously
1041 put Bytes in the FIFO*/
1042 (*descending_urgency="rl_data_read_phase,rl_read_request_from_AXI"*)
1043 (*descending_urgency="rl_data_read_phase,rl_write_request_from_AXI"*)
1044 rule rl_data_read_phase(rg_phase==DataRead_phase /*&& ccr_fmode!='b11*/ && transfer_cond && clock_cond && !qspi_flush);
1045 //rg_output_en<=0;
1046 if(half_cycle_delay || read_true) begin
1047 half_cycle_delay<=False;
1048 read_true <= False;
1049 end
1050 else begin
1051 Bit#(32) data_reg=dr;
1052 Bit#(32) count_byte=rg_count_bytes;
1053 Bit#(32) count_bits=rg_count_bits;
1054 Bit#(32) data_length1=(ccr_fmode=='b11)?mm_data_length:dlr;
1055 `ifdef verbose1 $display($time,"Executing DataRead Phase SPI Mode: %b DLR : %d Count_bits: %d Input :%b ccr_ddrm: %b",ccr_dmode,data_length1,rg_count_bits,rg_input,ccr_ddrm); `endif
1056 /* write incoming bit to the data register */
1057 if(ccr_dmode==1)begin // single line mode;
1058 data_reg=data_reg<<1;
1059 data_reg[0]=rg_input[1];
1060 `ifdef verbose $display($time,"Single data_reg : %b",data_reg); `endif
1061 count_bits=count_bits+1;
1062 rg_output_en <= 4'b1101;
1063 rg_output <= {1'b1,1'b0,1'b0,1'b0};
1064
1065 end
1066 else if(ccr_dmode==2)begin // dual line mode;
1067 rg_output_en <= 4'b1100;
1068 data_reg=data_reg<<2;
1069 data_reg[1:0]=rg_input[1:0];
1070 `ifdef verbose $display($time,"Dual data_reg : %b",data_reg); `endif
1071 count_bits=count_bits+1;
1072 rg_output <= {1'b1,1'b0,1'b0,1'b0};
1073 end
1074 else if(ccr_dmode==3) begin// quad line mode;
1075 rg_output_en <= 4'b0000;
1076 data_reg=data_reg<<4;
1077 data_reg[3:0]=rg_input;
1078 `ifdef verbose $display($time,"Quad data_reg : %b",data_reg); `endif
1079 count_bits=count_bits+1;
1080 end
1081
1082 /* write the last successfully received byte into the FIFO */
1083 if(ccr_dmode==1)begin// single line mode
1084 if(count_byte==data_length-1 && ccr_ddrm==1 && count_bits[2:0]=='b111) //To make sure that the Flash does not send any data the next half edge since ncs is made 1 after the second edge
1085 ncs<=1;
1086 if(rg_count_bits[2:0]=='b111)begin // multiple of eight bits have been read.
1087 `ifdef verbose1 $display("Enquing FIFO"); `endif
1088 Vector#(4,Bit#(8)) temp = newVector();
1089 temp[0]=data_reg[7:0];
1090 `ifdef verbose $display($time,"Single Enqueing FIFO : data is %h",temp[0]); `endif
1091 if(!first_read)
1092 fifo.enq(1,temp);
1093 count_byte=count_byte+1;
1094 end
1095 end
1096 else if(ccr_dmode==2) begin // dual line mode
1097 if(count_byte==data_length-1 && ccr_ddrm==1 && count_bits[1:0]=='b11) //To make sure that the Flash does not send any data the next half edge since ncs is made 1 after the second edge
1098 ncs<=1;
1099 if(rg_count_bits[1:0]=='b11)begin // multiple of eight bits have been read.
1100 `ifdef verbose1 $display("Enquing FIFO"); `endif
1101 Vector#(4,Bit#(8)) temp = newVector();
1102 temp[0]=data_reg[7:0];
1103 `ifdef verbose $display($time,"Dual Enqueing FIFO : data is %h",temp[0]); `endif
1104 if(!first_read)
1105 fifo.enq(1,temp);
1106 count_byte=count_byte+1;
1107 end
1108 end
1109 else if(ccr_dmode==3) begin // quad line mode
1110 if(count_byte==data_length-1 && ccr_ddrm==1 && count_bits[0]=='b1) //To make sure that the Flash does not send any data the next half edge since ncs is made 1 after the second edge
1111 ncs<=1;
1112 if(rg_count_bits[0]=='b1)begin // multiple of eight bits have been read.
1113 `ifdef verbose1 $display("Enquing FIFO"); `endif
1114 Vector#(4,Bit#(8)) temp = newVector();
1115 temp[0]=data_reg[7:0];
1116 `ifdef verbose $display($time,"Quad Enqueing FIFO : data is %h",temp[0]); `endif
1117 if(!first_read)
1118 fifo.enq(1,temp);
1119 count_byte=count_byte+1;
1120 end
1121 end
1122
1123 bit smf=0;
1124 `ifdef verbose $display("count_byte: %d data_length1: %d",count_byte,data_length1); `endif
1125 /* condition for termination of dataread_phase */
1126 if(data_length1!='hFFFFFFFF)begin // if limit is not undefined
1127 if(count_byte==data_length1)begin // if limit has bee reached.
1128 `ifdef verbose $display($time,"Limit has reached: rg_count_bytes %h data_length %h",count_byte,data_length); `endif
1129 if(ccr_fmode=='b10)begin // auto-status polling mode
1130 if(cr_pmm==0)begin // ANDed mode
1131 if((psmar&psmkr) == (psmkr&dr)) // is the unmasked bits match
1132 smf=1;
1133 else
1134 smf=0;
1135 end
1136 else begin// ORed mode
1137 let p=psmkr&dr;
1138 let q=psmkr&psmar;
1139 let r=~(p^q);
1140 if(|(r)==1)
1141 smf=1;
1142 else
1143 smf=0;
1144 end
1145 end
1146 else if(ccr_fmode=='b11)begin// memory mapped mode
1147 if(first_read) begin
1148 `ifdef verbose $display("Sending response back to the proc data_reg: %h",data_reg); `endif
1149 let r = AXI4_Lite_Rd_Data {rresp: AXI4_LITE_OKAY, rdata: duplicate(data_reg) , ruser: 0};
1150 s_xactor.i_rd_data.enq(r);
1151 first_read <= False;
1152 //rg_request_ready <= True;
1153 end
1154 end
1155 let {x,y,z}<-change_phase.func(rg_phase,rg_count_bits,smf);
1156 /* if(z==DataRead_phase)
1157 read_true <= True;*/
1158 rg_phase<=z;
1159 `ifdef verbose $display("rg_phase:",fshow(z),"sr_tcf: %d",y); `endif
1160 sr_tcf<=y; // set completion of transfer flag
1161 rg_count_bytes<=0;
1162 rg_count_bits<=0;
1163 end
1164 else begin
1165 rg_count_bytes<=count_byte;
1166 rg_count_bits<=count_bits;
1167 end
1168 end
1169 else if(dcr_fsize!='h1f)begin // if limit is not infinite
1170 Bit#(32) new_limit=1<<(dcr_fsize);
1171 `ifdef verbose1 $display("Sending completion -- newlimit : %h",new_limit); `endif
1172 if(truncate(rg_count_bytes)==new_limit)begin // if reached end of Flash memory
1173 let {x,y,z}<-change_phase.func(rg_phase,rg_count_bits,smf&cr_apms);
1174 rg_phase<=z;
1175 if(z==DataRead_phase)
1176 read_true <= True;
1177 sr_tcf<=y; // set completion of transfer flag
1178 rg_count_bytes<=0;
1179 rg_count_bits<=0;
1180 end
1181 else begin
1182 rg_count_bytes<=count_byte;
1183 rg_count_bits<=count_bits;
1184 end
1185 end
1186 else begin // keep looping untill abort signal is not raised.
1187 rg_count_bytes<=count_byte;
1188 rg_count_bits<=count_bits;
1189 end
1190 dr<=data_reg;
1191 sr_smf<=smf;
1192 end
1193 endrule
1194
1195 /* write data from the FIFO to the FLASH. Simulataneously*/
1196 (*descending_urgency="rl_data_write_phase,rl_read_request_from_AXI"*)
1197 (*descending_urgency="rl_data_write_phase,rl_write_request_from_AXI"*)
1198 rule rl_data_write_phase(rg_phase==DataWrite_phase && transfer_cond && clock_cond && !qspi_flush);
1199 if(half_cycle_delay)
1200 half_cycle_delay<=False;
1201 else begin
1202 Bit#(8) data_reg=fifo.first()[0];
1203 Bit#(32) count_byte=rg_count_bytes;
1204 Bit#(32) count_bits=rg_count_bits;
1205 Bit#(4) enable_o=0;
1206 /* write incoming bit to the data register */
1207 if(ccr_dmode==1)begin // single line mode;
1208 enable_o=4'b1101;
1209 rg_output<={1'b1,1'b0,1'b0,data_reg[rg_count_bits-1]};
1210 count_bits=count_bits-1;
1211 end
1212 else if(ccr_dmode==2)begin // dual line mode;
1213 enable_o=4'b1111;
1214 rg_output<={1'b1,1'b0,data_reg[rg_count_bits-1:rg_count_bits-2]};
1215 count_bits=count_bits-2;
1216 end
1217 else if(ccr_dmode==3) begin// quad line mode;
1218 enable_o=4'b1111;
1219 rg_output<=data_reg[rg_count_bits-1:rg_count_bits-4];
1220 count_bits=count_bits-4;
1221 end
1222 `ifdef verbose1 $display("Executing DataWrite Phase SPI Mode: %b DLR : %d Count_bits: %d Input :%b Enable: %b",ccr_dmode,dlr,rg_count_bits,rg_input,enable_o); `endif
1223
1224 /* write the last successfully received byte into the FIFO */
1225 if(ccr_dmode==1)begin// single line mode
1226 if(rg_count_bits==1)begin // multiple of eight bits have been read.
1227 fifo.deq(1);
1228 count_byte=count_byte+1;
1229 count_bits=8;
1230 end
1231 end
1232 else if(ccr_dmode==2) begin // dual line mode
1233 if(rg_count_bits==2)begin // multiple of eight bits have been read.
1234 fifo.deq(1);
1235 count_byte=count_byte+1;
1236 count_bits=8;
1237 end
1238 end
1239 else if(ccr_dmode==3) begin // quad line mode
1240 if(rg_count_bits==4)begin // multiple of eight bits have been read.
1241 fifo.deq(1);
1242 count_byte=count_byte+1;
1243 count_bits=8;
1244 end
1245 end
1246
1247 /* condition for termination of dataread_phase */
1248 if(dlr!='hFFFFFFFF)begin // if limit is not undefined
1249 if(rg_count_bytes==dlr)begin // if limit has bee reached.
1250 rg_phase<=Idle;
1251 sr_tcf<=1; // set completion of transfer flag
1252 rg_count_bytes<=0;
1253 rg_count_bits<=0;
1254 end
1255 else begin
1256 rg_count_bytes<=count_byte;
1257 rg_count_bits<=count_bits;
1258 end
1259 end
1260 else if(dcr_fsize!='h1f)begin // if limit is not infinite
1261 Bit#(32) new_limit=1<<(dcr_fsize);
1262 if(truncate(rg_count_bytes)==new_limit)begin // if reached end of Flash memory
1263 rg_phase<=Idle;
1264 sr_tcf<=1; // set completion of transfer flag
1265 rg_count_bytes<=0;
1266 rg_count_bits<=0;
1267 end
1268 else begin
1269 rg_count_bytes<=count_byte;
1270 rg_count_bits<=count_bits;
1271 end
1272 end
1273 else begin // keep looping untill abort signal is not raised.
1274 rg_count_bytes<=count_byte;
1275 rg_count_bits<=count_bits;
1276 end
1277 rg_output_en<=enable_o;
1278 end
1279 endrule
1280
1281 rule display_all_Registers;
1282 `ifdef verbose1 $display($time,"\tPhase: ",fshow(rg_phase)," CR WRitten %d",wr_instruction_written, "Address Written: %d",wr_address_written); `endif
1283 `ifdef verbose1 $display($time,"\tCR: %h\tDCR: %h\tSR: %h\tFCR: %h",cr,dcr,sr,fcr); `endif
1284 `ifdef verbose1 $display($time,"\tDLR: %h\tCCR: %h\tAR: %h\tABR: %h",dlr,ccr,ar,abr); `endif
1285 `ifdef verbose1 $display($time,"\tDR: %h\tPSMKR: %h\tPSMAR: %h\tPIR: %h",dr,psmkr,psmar,pir,"\n"); `endif
1286 endrule
1287
1288 `ifdef simulate
1289 rule delay_phase(((wr_sdr_clock && ccr_ddrm==0) || (ddr_clock && ccr_ddrm==1)));
1290 rg_phase_delayed<=rg_phase;
1291 endrule
1292 `endif
1293
1294 interface QSPI_out out;
1295 method Bit#(9) io0_sdio_ctrl;
1296 return sdio0r[8:0];
1297 endmethod
1298 method Bit#(9) io1_sdio_ctrl;
1299 return sdio1r[8:0];
1300 endmethod
1301 method Bit#(9) io2_sdio_ctrl;
1302 return sdio2r[8:0];
1303 endmethod
1304 method Bit#(9) io3_sdio_ctrl;
1305 return sdio3r[8:0];
1306 endmethod
1307 interface clk_o = interface Get
1308 method ActionValue#(Bit#(1)) get;
1309 return delay_ncs==1?dcr_ckmode:rg_clk;
1310 endmethod
1311 endinterface;
1312 interface io_out = interface Get
1313 method ActionValue#(Bit#(4)) get;
1314 return rg_output;
1315 endmethod
1316 endinterface;
1317 interface io_out_en = interface Get
1318 method ActionValue#(Bit#(4)) get;
1319 return rg_output_en;
1320 endmethod
1321 endinterface;
1322 interface io_in = interface Put
1323 method Action put(Bit#(4) in);
1324 rg_input<=in;
1325 endmethod
1326 endinterface;
1327 interface ncs_o = interface Get
1328 method ActionValue#(Bit#(1)) get;
1329 return ncs;
1330 endmethod
1331 endinterface;
1332 endinterface
1333
1334 interface slave= s_xactor.axi_side;
1335
1336 method Bit#(6) interrupts; // 0=TOF, 1=SMF, 2=Threshold, 3=TCF, 4=TEF 5=request_ready
1337 return {pack(rg_request_ready),sr_tef&cr_teie, sr_tcf&cr_tcie, sr_ftf&cr_ftie, sr_smf&cr_smie , sr_tof&cr_toie};
1338 endmethod
1339 `ifdef simulate method curphase = rg_phase_delayed; `endif
1340 endmodule
1341
1342 endpackage
Unnamed repository; edit this file 'description' to name the repository.