src/peripherals/rgbttl/rgbttl_dummy.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras All rights reserved.
   3
   4 Redistribution and use in source and binary forms, with or without modification, are permitted
   5 provided that the following conditions are met:
   6
   7 * Redistributions of source code must retain the above copyright notice, this list of conditions
   8   and the following disclaimer.
   9 * Redistributions in binary form must reproduce the above copyright notice, this list of
  10   conditions and the following disclaimer in the documentation and/or other materials provided
  11  with the distribution.
  12 * Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or
  13   promote products derived from this software without specific prior written permission.
  14
  15 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
  16 OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
  17 AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
  18 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  20 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  21 IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  22 OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23 --------------------------------------------------------------------------------------------------
  24
  25 Author: Neel Gala
  26 Email id: neelgala@gmail.com
  27 Details:
  28
  29 --------------------------------------------------------------------------------------------------
  30 */
  31 package rgbttl_dummy;
  32   `define RGBTTL_WIDTH 18
  33   `include "instance_defines.bsv"
  34   import ClockDiv::*;
  35   import ConcatReg::*;
  36   import Semi_FIFOF::*;
  37   import BUtils ::*;
  38   import AXI4_Lite_Types::*;
  39
  40   interface Ifc_rgbttl_dummy;
  41           interface AXI4_Lite_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
  42     method  Bit#(1) de;
  43     method  Bit#(1) ck;
  44     method  Bit#(1) vs;
  45     method  Bit#(1) hs;
  46     method  Bit#(`RGBTTL_WIDTH) data;
  47   endinterface
  48
  49   (*synthesize*)
  50   module mkrgbttl_dummy(Ifc_rgbttl_dummy);
  51                 AXI4_Lite_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
  52                             s_xactor<-mkAXI4_Lite_Slave_Xactor();
  53
  54       Reg#(Bit#(1)) rg_de <- mkReg(0);
  55       Reg#(Bit#(1)) rg_ck <- mkReg(0);
  56       Reg#(Bit#(1)) rg_vs <- mkReg(0);
  57       Reg#(Bit#(1)) rg_hs <- mkReg(0);
  58       Reg#(Bit#(`RGBTTL_WIDTH)) rg_data <- mkReg(0);
  59
  60     method  de = rg_de;
  61     method  ck = rg_ck;
  62     method  vs = rg_vs;
  63     method  hs = rg_hs;
  64     method  data = rg_data;
  65     interface slave=s_xactor.axi_side;
  66   endmodule
  67 endpackage