adding master and slave interface to rgbtll
[shakti-peripherals.git] / src / peripherals / rgbttl / rgbttl_dummy.bsv
1 /*
2 Copyright (c) 2013, IIT Madras All rights reserved.
3
4 Redistribution and use in source and binary forms, with or without modification, are permitted
5 provided that the following conditions are met:
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8 and the following disclaimer.
9 * Redistributions in binary form must reproduce the above copyright notice, this list of
10 conditions and the following disclaimer in the documentation and/or other materials provided
11 with the distribution.
12 * Neither the name of IIT Madras nor the names of its contributors may be used to endorse or
13 promote products derived from this software without specific prior written permission.
14
15 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
16 OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
17 AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
18 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
21 IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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23 --------------------------------------------------------------------------------------------------
24
25 Author: Neel Gala
26 Email id: neelgala@gmail.com
27 Details:
28
29 --------------------------------------------------------------------------------------------------
30 */
31 package rgbttl_dummy;
32 `define RGBTTL_WIDTH 18
33 `include "instance_defines.bsv"
34 import GetPut::*;
35 import BUtils ::*;
36 import AXI4_Types::*;
37
38 interface Ifc_rgbttl_dummy;
39 interface AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
40 interface AXI4_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
41 interface Get#(Bit#(1)) de;
42 interface Get#(Bit#(1)) ck;
43 interface Get#(Bit#(1)) vs;
44 interface Get#(Bit#(1)) hs;
45 interface Get#(Bit#(`RGBTTL_WIDTH)) data_out;
46 endinterface
47
48 (*synthesize*)
49 module mkrgbttl_dummy(Ifc_rgbttl_dummy);
50 AXI4_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
51 s_xactor<-mkAXI4_Slave_Xactor();
52 AXI4_Master_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
53 m_xactor<-mkAXI4_Master_Xactor();
54
55 Reg#(Bit#(1)) rg_de <- mkReg(0);
56 Reg#(Bit#(1)) rg_ck <- mkReg(0);
57 Reg#(Bit#(1)) rg_vs <- mkReg(0);
58 Reg#(Bit#(1)) rg_hs <- mkReg(0);
59 Reg#(Bit#(`RGBTTL_WIDTH)) rg_data <- mkReg(0);
60
61 interface de = interface Get
62 method ActionValue#(Bit#(1)) get;
63 return rg_de;
64 endmethod
65 endinterface;
66
67 interface ck = interface Get
68 method ActionValue#(Bit#(1)) get;
69 return rg_ck;
70 endmethod
71 endinterface;
72
73 interface vs = interface Get
74 method ActionValue#(Bit#(1)) get;
75 return rg_vs;
76 endmethod
77 endinterface;
78
79 interface hs = interface Get
80 method ActionValue#(Bit#(1)) get;
81 return rg_hs;
82 endmethod
83 endinterface;
84
85 interface data_out = interface Get
86 method ActionValue#(Bit#(`RGBTTL_WIDTH)) get;
87 return rg_data;
88 endmethod
89 endinterface;
90
91 interface slave=s_xactor.axi_side;
92 interface master=m_xactor.axi_side;
93 endmodule
94 endpackage