src/peripherals/uart/RS232_modified.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 ////////////////////////////////////////////////////////////////////////////////
  15 // Copyright (c) 2010  Bluespec, Inc.   ALL RIGHTS RESERVED.
  16 ////////////////////////////////////////////////////////////////////////////////
  17 //  Filename      : RS232.bsv
  18 //  Description   : Simple UART BFM   RS232 <-> Bit#(8)
  19 ////////////////////////////////////////////////////////////////////////////////
  20 package RS232_modified;
  21
  22 // Notes :
  23
  24 ////////////////////////////////////////////////////////////////////////////////
  25 /// Imports
  26 ////////////////////////////////////////////////////////////////////////////////
  27 import Clocks            ::*;
  28 import GetPut            ::*;
  29 import Connectable       ::*;
  30 import FIFOLevel         ::*;
  31 import Vector            ::*;
  32 import BUtils            ::*;
  33 import Counter           ::*;
  34
  35 ////////////////////////////////////////////////////////////////////////////////
  36 /// Exports
  37 ////////////////////////////////////////////////////////////////////////////////
  38 export RS232             (..);
  39 export UART              (..);
  40 export BaudGenerator     (..);
  41 export Parity            (..);
  42 export StopBits          (..);
  43 export InputFilter       (..);
  44 export Synchronizer      (..);
  45 export EdgeDetector      (..);
  46 export InputMovingFilter (..);
  47 export mkUART;
  48 export mkBaudGenerator;
  49 export mkInputFilter;
  50 export mkSynchronizer;
  51 export mkEdgeDetector;
  52 export mkInputMovingFilter;
  53
  54 ////////////////////////////////////////////////////////////////////////////////
  55 /// Types
  56 ////////////////////////////////////////////////////////////////////////////////
  57 typedef union tagged {
  58    void Start;
  59    void Center;
  60    void Wait;
  61    void Sample;
  62    void Parity;
  63    void StopFirst;
  64    void StopLast;
  65    } RecvState deriving (Bits, Eq);
  66
  67 typedef union tagged {
  68    void Idle;
  69    void Start;
  70    void Wait;
  71    void Shift;
  72    void Stop;
  73    void Stop5;
  74    void Stop2;
  75    void Parity;
  76    } XmitState deriving (Bits, Eq);
  77
  78 typedef enum {
  79    NONE,
  80    ODD,
  81    EVEN
  82    } Parity deriving (Bits, Eq);
  83
  84 typedef enum {
  85    STOP_1,
  86    STOP_1_5,
  87    STOP_2
  88    } StopBits deriving (Bits, Eq);
  89
  90 ////////////////////////////////////////////////////////////////////////////////
  91 /// Interfaces
  92 ////////////////////////////////////////////////////////////////////////////////
  93 (* always_ready, always_enabled *)
  94 interface RS232;
  95    // Inputs
  96    (* prefix = "" *)
  97    method    Action      sin((* port = "SIN" *)Bit#(1) x);
  98    // Outputs
  99    (* prefix = "", result = "SOUT" *)
 100    method    Bit#(1)     sout();
 101 endinterface
 102
 103 interface BaudGenerator;
 104    method    Action    clock_enable();
 105    method    Action    clear();
 106    method    Bool      baud_tick_16x();
 107    method    Bool      baud_tick_2x();
 108 endinterface
 109
 110 interface InputFilter#(numeric type size, type a);
 111    method    Action    clock_enable();
 112    method    a         _read();
 113 endinterface
 114
 115 (* always_ready, always_enabled *)
 116 interface EdgeDetector#(type a);
 117    method    Bool      rising();
 118    method    Bool      falling();
 119 endinterface
 120
 121 (* always_ready, always_enabled *)
 122 interface Synchronizer#(type a);
 123    method    Action    _write(a x);
 124    method    a         _read();
 125 endinterface
 126
 127 interface InputMovingFilter#(numeric type width, numeric type threshold, type a);
 128    method    Action    sample();
 129    method    Action    clear();
 130    method    a         _read();
 131 endinterface
 132
 133 interface UART#(numeric type depth);
 134    (* prefix = "" *)
 135    interface RS232           rs232;
 136    interface Get#(Bit#(8))   tx;
 137    interface Put#(Bit#(8))   rx;
 138    method Bool transmission_done;
 139    method Bool receiver_not_empty;
 140    method Bool receiver_not_full;
 141    method Bool transmittor_not_empty;
 142 endinterface
 143
 144
 145 ////////////////////////////////////////////////////////////////////////////////
 146 ////////////////////////////////////////////////////////////////////////////////
 147 ///
 148 /// Implementation of Baud Generator
 149 ///
 150 ////////////////////////////////////////////////////////////////////////////////
 151 ////////////////////////////////////////////////////////////////////////////////
 152 module mkBaudGenerator#(Bit#(16) divider)(BaudGenerator);
 153
 154    ////////////////////////////////////////////////////////////////////////////////
 155    /// Design Elements
 156    ////////////////////////////////////////////////////////////////////////////////
 157    Counter#(16)                              rBaudCounter        <- mkCounter(0);
 158    PulseWire                                 pwBaudTick16x       <- mkPulseWire;
 159
 160    Counter#(3)                               rBaudTickCounter    <- mkCounter(0);
 161    PulseWire                                 pwBaudTick2x        <- mkPulseWire;
 162
 163    Wire#(Bit#(16))                           wBaudCount          <- mkWire;
 164    rule baud_count_wire;
 165       wBaudCount <= rBaudCounter.value;
 166    endrule
 167    Wire#(Bit#(3))                            wBaudTickCount      <- mkWire;
 168    rule baud_tick_count_wire;
 169       wBaudTickCount <= rBaudTickCounter.value;
 170    endrule
 171
 172    ////////////////////////////////////////////////////////////////////////////////
 173    /// Rules
 174    ////////////////////////////////////////////////////////////////////////////////
 175    rule count_baudtick_16x(pwBaudTick16x);
 176       rBaudTickCounter.up;
 177    endrule
 178
 179    rule assert_2x_baud_tick(rBaudTickCounter.value() == 0 && pwBaudTick16x);
 180       pwBaudTick2x.send;
 181    endrule
 182
 183    ////////////////////////////////////////////////////////////////////////////////
 184    /// Interface Connections / Methods
 185    ////////////////////////////////////////////////////////////////////////////////
 186    method Action clock_enable();
 187       if (rBaudCounter.value() + 1 >= divider) begin
 188          pwBaudTick16x.send;
 189          rBaudCounter.clear;
 190       end
 191       else begin
 192          rBaudCounter.up;
 193       end
 194    endmethod
 195
 196    method Action clear();
 197       rBaudCounter.clear;
 198    endmethod
 199
 200    method Bool baud_tick_16x();
 201       return pwBaudTick16x;
 202    endmethod
 203
 204    method Bool baud_tick_2x();
 205       return pwBaudTick2x;
 206    endmethod
 207
 208 endmodule: mkBaudGenerator
 209
 210 ////////////////////////////////////////////////////////////////////////////////
 211 ////////////////////////////////////////////////////////////////////////////////
 212 ///
 213 /// Implementation of Input Filter
 214 ///
 215 ////////////////////////////////////////////////////////////////////////////////
 216 ////////////////////////////////////////////////////////////////////////////////
 217 module mkInputFilter#(a initval, a din)(InputFilter#(size, a))
 218    provisos( Bits#(a, sa)
 219            , Eq#(a)
 220            , Add#(0, sa, 1)
 221            , Log#(size, logsize)
 222            , Add#(logsize, 1, csize)
 223            );
 224
 225    ////////////////////////////////////////////////////////////////////////////////
 226    /// Design Elements
 227    ////////////////////////////////////////////////////////////////////////////////
 228    Counter#(csize)                           counter             <- mkCounter(0);
 229    Reg#(a)                                   rOut                <- mkReg(initval);
 230
 231    ////////////////////////////////////////////////////////////////////////////////
 232    /// Rules
 233    ////////////////////////////////////////////////////////////////////////////////
 234
 235    ////////////////////////////////////////////////////////////////////////////////
 236    /// Interface Connections / Methods
 237    ////////////////////////////////////////////////////////////////////////////////
 238    method Action clock_enable();
 239       if (din == unpack(1) && counter.value() != fromInteger(valueof(size)))
 240          counter.up;
 241       else if (din == unpack(0) && counter.value() != 0)
 242          counter.down;
 243
 244       if (counter.value() == fromInteger(valueof(size)))
 245          rOut <= unpack(1);
 246       else if (counter.value() == 0)
 247          rOut <= unpack(0);
 248    endmethod
 249
 250    method a _read;
 251       return rOut;
 252    endmethod
 253
 254 endmodule
 255
 256
 257 ////////////////////////////////////////////////////////////////////////////////
 258 ////////////////////////////////////////////////////////////////////////////////
 259 ///
 260 /// Implementation
 261 ///
 262 ////////////////////////////////////////////////////////////////////////////////
 263 ////////////////////////////////////////////////////////////////////////////////
 264 module mkEdgeDetector#(a initval, a din)(EdgeDetector#(a))
 265    provisos( Bits#(a, sa)
 266            , Eq#(a)
 267            , Add#(0, sa, 1)
 268            );
 269
 270    ////////////////////////////////////////////////////////////////////////////////
 271    /// Design Elements
 272    ////////////////////////////////////////////////////////////////////////////////
 273    Reg#(a)                                   rDinD1              <- mkReg(initval);
 274
 275    ////////////////////////////////////////////////////////////////////////////////
 276    /// Rules
 277    ////////////////////////////////////////////////////////////////////////////////
 278    (* fire_when_enabled *)
 279    (* no_implicit_conditions *)
 280    rule pipeline;
 281       rDinD1 <= din;
 282    endrule
 283
 284    ////////////////////////////////////////////////////////////////////////////////
 285    /// Interface Connections / Methods
 286    ////////////////////////////////////////////////////////////////////////////////
 287    method Bool rising();
 288       return (din == unpack(1) && rDinD1 == unpack(0));
 289    endmethod
 290
 291    method Bool falling();
 292       return (din == unpack(0) && rDinD1 == unpack(1));
 293    endmethod
 294
 295 endmodule: mkEdgeDetector
 296
 297 ////////////////////////////////////////////////////////////////////////////////
 298 ///
 299 ////////////////////////////////////////////////////////////////////////////////
 300 function Bool getRising(EdgeDetector#(a) ifc);
 301    return ifc.rising;
 302 endfunction
 303
 304 function Bool getFalling(EdgeDetector#(a) ifc);
 305    return ifc.falling;
 306 endfunction
 307
 308 ////////////////////////////////////////////////////////////////////////////////
 309 ////////////////////////////////////////////////////////////////////////////////
 310 ///
 311 /// Implementation of Synchronizer
 312 ///
 313 ////////////////////////////////////////////////////////////////////////////////
 314 ////////////////////////////////////////////////////////////////////////////////
 315 module mkSynchronizer#(a initval)(Synchronizer#(a))
 316    provisos( Bits#(a, sa)
 317            , Add#(0, sa, 1)
 318            );
 319
 320    ////////////////////////////////////////////////////////////////////////////////
 321    /// Design Elements
 322    ////////////////////////////////////////////////////////////////////////////////
 323    Reg#(a)                                   d1                  <- mkReg(initval);
 324    Reg#(a)                                   d2                  <- mkReg(initval);
 325
 326    ////////////////////////////////////////////////////////////////////////////////
 327    /// Interface Connections / Methods
 328    ////////////////////////////////////////////////////////////////////////////////
 329    method Action _write(x);
 330       d1 <= x;
 331       d2 <= d1;
 332    endmethod
 333
 334    method a _read();
 335       return d2;
 336    endmethod
 337
 338 endmodule: mkSynchronizer
 339
 340 ////////////////////////////////////////////////////////////////////////////////
 341 ////////////////////////////////////////////////////////////////////////////////
 342 ///
 343 /// Implementation of Input Filter
 344 ///
 345 ////////////////////////////////////////////////////////////////////////////////
 346 ////////////////////////////////////////////////////////////////////////////////
 347 module mkInputMovingFilter#(a din)(InputMovingFilter#(width, threshold, a))
 348    provisos( Bits#(a, sa)
 349            , Eq#(a)
 350            , Add#(0, sa, 1)
 351            );
 352
 353    ////////////////////////////////////////////////////////////////////////////////
 354    /// Design Elements
 355    ////////////////////////////////////////////////////////////////////////////////
 356    Counter#(width)                           counter             <- mkCounter(0);
 357    Reg#(a)                                   rOut                <- mkReg(unpack(0));
 358    PulseWire                                 pwSample            <- mkPulseWire;
 359
 360    ////////////////////////////////////////////////////////////////////////////////
 361    /// Rules
 362    ////////////////////////////////////////////////////////////////////////////////
 363    (* preempts = "threshold_compare, take_sample" *)
 364    rule threshold_compare(counter.value() >= fromInteger(valueof(threshold)));
 365       rOut <= unpack(1);
 366    endrule
 367
 368    rule take_sample(pwSample && din == unpack(1));
 369       counter.up;
 370    endrule
 371
 372    ////////////////////////////////////////////////////////////////////////////////
 373    /// Interface Connections / Methods
 374    ////////////////////////////////////////////////////////////////////////////////
 375    method Action sample();
 376       pwSample.send;
 377    endmethod
 378
 379    method Action clear();
 380       counter.clear();
 381       rOut <= unpack(0);
 382    endmethod
 383
 384    method a _read;
 385       return rOut;
 386    endmethod
 387
 388 endmodule
 389
 390
 391 ////////////////////////////////////////////////////////////////////////////////
 392 ////////////////////////////////////////////////////////////////////////////////
 393 ///
 394 /// Implementation of UART
 395 ///
 396 ////////////////////////////////////////////////////////////////////////////////
 397 ////////////////////////////////////////////////////////////////////////////////
 398 module mkUART( Bit#(4) charsize
 399              , Parity paritysel
 400              , StopBits stopbits
 401              , Bit#(16) divider
 402              , UART#(d) ifc)
 403    provisos(Add#(2, _1, d));
 404
 405    Integer fifodepth = valueof(d);
 406
 407    ////////////////////////////////////////////////////////////////////////////////
 408    /// Design Elements
 409    ////////////////////////////////////////////////////////////////////////////////
 410    let                                       baudGen               <- mkBaudGenerator( divider );
 411
 412    ////////////////////////////////////////////////////////////////////////////////
 413    /// Receive UART
 414    ////////////////////////////////////////////////////////////////////////////////
 415    FIFOLevelIfc#(Bit#(8), d)                 fifoRecv              <- mkGFIFOLevel(True, False, True);
 416
 417    Vector#(8, Reg#(Bit#(1)))                 vrRecvBuffer          <- replicateM(mkRegU);
 418
 419    Reg#(Bit#(1))                             rRecvData             <- mkReg(1);
 420
 421    Reg#(RecvState)                           rRecvState            <- mkRegA(Start);
 422    Reg#(Bit#(4))                             rRecvCellCount        <- mkRegA(0);
 423    Reg#(Bit#(4))                             rRecvBitCount         <- mkRegA(0);
 424    Reg#(Bit#(1))                             rRecvParity           <- mkRegA(0);
 425
 426    PulseWire                                 pwRecvShiftBuffer     <- mkPulseWire;
 427    PulseWire                                 pwRecvCellCountReset  <- mkPulseWire;
 428    PulseWire                                 pwRecvResetBitCount   <- mkPulseWire;
 429    PulseWire                                 pwRecvEnableBitCount  <- mkPulseWire;
 430
 431    ////////////////////////////////////////////////////////////////////////////////
 432    /// Transmit UART
 433    ////////////////////////////////////////////////////////////////////////////////
 434    FIFOLevelIfc#(Bit#(8), d)                 fifoXmit              <- mkGFIFOLevel(False, False, True);
 435
 436    Vector#(8, Reg#(Bit#(1)))                 vrXmitBuffer          <- replicateM(mkRegU);
 437
 438    Reg#(XmitState)                           rXmitState            <- mkRegA(Idle);
 439    Reg#(Bit#(4))                             rXmitCellCount        <- mkRegA(0);
 440    Reg#(Bit#(4))                             rXmitBitCount         <- mkRegA(0);
 441    Reg#(Bit#(1))                             rXmitDataOut          <- mkRegA(1);
 442    Reg#(Bit#(1))                             rXmitParity           <- mkRegA(0);
 443
 444    PulseWire                                 pwXmitCellCountReset  <- mkPulseWire;
 445    PulseWire                                 pwXmitResetBitCount   <- mkPulseWire;
 446    PulseWire                                 pwXmitEnableBitCount  <- mkPulseWire;
 447    PulseWire                                 pwXmitLoadBuffer      <- mkPulseWire;
 448    PulseWire                                 pwXmitShiftBuffer     <- mkPulseWire;
 449
 450    ////////////////////////////////////////////////////////////////////////////////
 451    /// Definitions
 452    ////////////////////////////////////////////////////////////////////////////////
 453    let tick               = baudGen.baud_tick_16x;
 454
 455    ////////////////////////////////////////////////////////////////////////////////
 456    /// Baud Clock Enable
 457    ////////////////////////////////////////////////////////////////////////////////
 458    (* no_implicit_conditions, fire_when_enabled *)
 459    rule baud_generator_clock_enable;
 460       baudGen.clock_enable;
 461    endrule
 462
 463    ////////////////////////////////////////////////////////////////////////////////
 464    /// Receive Rules
 465    ////////////////////////////////////////////////////////////////////////////////
 466    rule receive_bit_cell_time_counter(tick);
 467       if (pwRecvCellCountReset)
 468          rRecvCellCount <= 0;
 469       else
 470          rRecvCellCount <= rRecvCellCount + 1;
 471    endrule
 472
 473    rule receive_buffer_shift(pwRecvShiftBuffer);
 474       let v = shiftInAtN(readVReg(vrRecvBuffer), rRecvData);
 475       writeVReg(vrRecvBuffer, v);
 476    endrule
 477
 478    rule receive_bit_counter;
 479       if (pwRecvResetBitCount)
 480          rRecvBitCount <= 0;
 481       else if (pwRecvEnableBitCount)
 482          rRecvBitCount <= rRecvBitCount + 1;
 483    endrule
 484
 485    rule receive_wait_for_start_bit(rRecvState == Start && tick);
 486       pwRecvCellCountReset.send();
 487       if (rRecvData == 1'b0) begin
 488          rRecvState <= Center;
 489       end
 490       else begin
 491          rRecvState <= Start;
 492          pwRecvResetBitCount.send();
 493       end
 494    endrule
 495
 496    rule receive_find_center_of_bit_cell(rRecvState == Center && tick);
 497       if (rRecvCellCount == 4'h4) begin
 498          pwRecvCellCountReset.send();
 499          if (rRecvData == 1'b0)
 500             rRecvState <= Wait;
 501          else
 502             rRecvState <= Start;
 503       end
 504       else begin
 505          rRecvState <= Center;
 506       end
 507    endrule
 508
 509    rule receive_wait_bit_cell_time_for_sample(rRecvState == Wait && rRecvCellCount == 4'hF && tick);
 510       pwRecvCellCountReset.send;
 511
 512       if (rRecvBitCount == charsize) begin
 513          if (paritysel != NONE)
 514             rRecvState <= Parity;
 515          else if (stopbits != STOP_1)
 516             rRecvState <= StopFirst;
 517          else
 518             rRecvState <= StopLast;
 519       end
 520       else if (rRecvBitCount == charsize + 1) begin
 521          if (paritysel == NONE || stopbits == STOP_1)
 522             rRecvState <= StopLast;
 523          else
 524             rRecvState <= StopFirst;
 525       end
 526       else if (rRecvBitCount == charsize + 2) begin
 527          rRecvState <= StopLast;
 528       end
 529       else begin
 530          rRecvState <= Sample;
 531       end
 532    endrule
 533
 534    rule receive_sample_pin(rRecvState == Sample && tick);
 535       pwRecvShiftBuffer.send;
 536       pwRecvEnableBitCount.send;
 537       pwRecvCellCountReset.send;
 538       rRecvState <= Wait;
 539    endrule
 540
 541    rule receive_parity_bit(rRecvState == Parity && tick);
 542       rRecvParity <= rRecvData;
 543       pwRecvEnableBitCount.send;
 544       pwRecvCellCountReset.send;
 545       rRecvState <= Wait;
 546    endrule
 547
 548    rule receive_stop_first_bit(rRecvState == StopFirst && tick);
 549       pwRecvEnableBitCount.send;
 550       pwRecvCellCountReset.send;
 551       if (rRecvData == 1)
 552          rRecvState <= Wait;
 553       else
 554          rRecvState <= Start;
 555    endrule
 556
 557    rule receive_stop_last_bit(rRecvState == StopLast && tick);
 558       Vector#(8, Bit#(1)) data = take(readVReg(vrRecvBuffer));
 559       Bit#(8)          bitdata = pack(data) >> (8 - charsize);
 560
 561       fifoRecv.enq(bitdata);
 562       rRecvState <= Start;
 563       pwRecvCellCountReset.send;
 564    endrule
 565
 566    ////////////////////////////////////////////////////////////////////////////////
 567    /// Transmit Rules
 568    ////////////////////////////////////////////////////////////////////////////////
 569    rule transmit_bit_cell_time_counter(tick);
 570       if (pwXmitCellCountReset)
 571          rXmitCellCount <= 0;
 572       else
 573          rXmitCellCount <= rXmitCellCount + 1;
 574    endrule
 575
 576    rule transmit_bit_counter;
 577       if (pwXmitResetBitCount)
 578          rXmitBitCount <= 0;
 579       else if (pwXmitEnableBitCount)
 580          rXmitBitCount <= rXmitBitCount + 1;
 581    endrule
 582
 583    rule transmit_buffer_load(pwXmitLoadBuffer);
 584       Bit#(8) data = pack(fifoXmit.first);
 585       fifoXmit.deq;
 586
 587       writeVReg(vrXmitBuffer, unpack(data));
 588       rXmitParity <= parity(data);
 589    endrule
 590
 591    rule transmit_buffer_shift(!pwXmitLoadBuffer && pwXmitShiftBuffer);
 592       let v = shiftInAtN(readVReg(vrXmitBuffer), 1);
 593       writeVReg(vrXmitBuffer, v);
 594    endrule
 595
 596    rule transmit_wait_for_start_command(rXmitState == Idle && tick);
 597       rXmitDataOut <= 1'b1;
 598       pwXmitResetBitCount.send;
 599       if (fifoXmit.notEmpty) begin
 600          pwXmitCellCountReset.send;
 601          pwXmitLoadBuffer.send;
 602          rXmitState <= Start;
 603       end
 604       else begin
 605          rXmitState <= Idle;
 606       end
 607    endrule
 608
 609    rule transmit_send_start_bit(rXmitState == Start && tick);
 610       rXmitDataOut <= 1'b0;
 611       if (rXmitCellCount == 4'hF) begin
 612          rXmitState <= Wait;
 613          pwXmitCellCountReset.send;
 614       end
 615       else begin
 616          rXmitState <= Start;
 617       end
 618    endrule
 619
 620    rule transmit_wait_1_bit_cell_time(rXmitState == Wait && tick);
 621       rXmitDataOut <= head(readVReg(vrXmitBuffer));
 622       if (rXmitCellCount == 4'hF) begin
 623          pwXmitCellCountReset.send;
 624          if (rXmitBitCount == (charsize - 1) && (paritysel == NONE)) begin
 625             rXmitState <= Stop;
 626          end
 627          else if (rXmitBitCount == (charsize - 1) && (paritysel != NONE)) begin
 628             rXmitState <= Parity;
 629          end
 630          else begin
 631             rXmitState <= Shift;
 632             pwXmitEnableBitCount.send;
 633          end
 634       end
 635       else begin
 636          rXmitState <= Wait;
 637       end
 638    endrule
 639
 640    rule transmit_shift_next_bit(rXmitState == Shift && tick);
 641       rXmitDataOut <= head(readVReg(vrXmitBuffer));
 642       rXmitState  <= Wait;
 643       pwXmitShiftBuffer.send;
 644    endrule
 645
 646    rule transmit_send_parity_bit(rXmitState == Parity && tick);
 647       case(paritysel) matches
 648          ODD:        rXmitDataOut <= rXmitParity;
 649          EVEN:       rXmitDataOut <= ~rXmitParity;
 650          default:    rXmitDataOut <= 1'b0;
 651       endcase
 652
 653       if (rXmitCellCount == 4'hF) begin
 654          rXmitState   <= Stop;
 655          pwXmitCellCountReset.send;
 656       end
 657       else begin
 658          rXmitState   <= Parity;
 659       end
 660    endrule
 661
 662    rule transmit_send_stop_bit(rXmitState == Stop && tick);
 663       rXmitDataOut <= 1'b1;
 664       if (rXmitCellCount == 4'hF && (stopbits == STOP_1)) begin
 665          rXmitState <= Idle;
 666          pwXmitCellCountReset.send;
 667       end
 668       else if (rXmitCellCount == 4'hF && (stopbits == STOP_2)) begin
 669          rXmitState <= Stop2;
 670          pwXmitCellCountReset.send;
 671       end
 672       else if (rXmitCellCount == 4'hF && (stopbits == STOP_1_5)) begin
 673          rXmitState <= Stop5;
 674          pwXmitCellCountReset.send;
 675       end
 676       else begin
 677          rXmitState <= Stop;
 678       end
 679    endrule
 680
 681    rule transmit_send_stop_bit1_5(rXmitState == Stop5 && tick);
 682       rXmitDataOut <= 1'b1;
 683       if (rXmitCellCount == 4'h7) begin
 684          rXmitState <= Idle;
 685          pwXmitCellCountReset.send;
 686       end
 687       else begin
 688          rXmitState <= Stop5;
 689       end
 690    endrule
 691
 692    rule transmit_send_stop_bit2(rXmitState == Stop2 && tick);
 693       rXmitDataOut <= 1'b1;
 694       if (rXmitCellCount == 4'hF) begin
 695          rXmitState <= Idle;
 696          pwXmitCellCountReset.send;
 697       end
 698       else begin
 699          rXmitState <= Stop2;
 700       end
 701    endrule
 702
 703    ////////////////////////////////////////////////////////////////////////////////
 704    /// Interface Connections / Methods
 705    ////////////////////////////////////////////////////////////////////////////////
 706    interface RS232 rs232;
 707       method sout    = rXmitDataOut;
 708       method sin     = rRecvData._write;
 709    endinterface
 710
 711    interface Get tx;
 712       method ActionValue#(Bit#(8)) get;
 713          let data = pack(fifoRecv.first);
 714          fifoRecv.deq;
 715          return data;
 716       endmethod
 717    endinterface
 718
 719    interface Put rx;
 720       method Action put(x);
 721          fifoXmit.enq(x);
 722       endmethod
 723    endinterface
 724
 725    method Bool transmission_done;
 726            if(!fifoXmit.notEmpty && rXmitState==Idle)
 727               return True;
 728            else
 729               return False;
 730    endmethod
 731
 732    method Bool receiver_not_empty;
 733       return fifoRecv.notEmpty();
 734    endmethod
 735
 736    method Bool receiver_not_full;
 737           return fifoRecv.notFull();
 738    endmethod
 739
 740    method Bool transmittor_not_empty;
 741           return fifoXmit.notEmpty();
 742    endmethod
 743 endmodule
 744
 745
 746 endpackage
 747