src/peripherals/uart/Uart_bs.bsv

   1
   2 /*
   3 Copyright (c) 2013, IIT Madras
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   7
   8 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   9 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  10 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  11
  12 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  13 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  14
  15 Description: Bluespec UART with an AXI interface.
  16 */
  17 package Uart_bs;
  18
  19         `define Depth 16
  20
  21         import defined_types::*;
  22         import AXI4_Lite_Types::*;
  23         import AXI4_Lite_Fabric::*;
  24         import Semi_FIFOF::*;
  25         `include "instance_defines.bsv"
  26         import RS232_modified::*;
  27         import GetPut::*;
  28         import FIFO::*;
  29         import Clocks::*;
  30
  31
  32         interface Ifc_Uart_bs;
  33                 interface AXI4_Lite_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) slave_axi_uart;
  34                 interface RS232 coe_rs232;
  35         endinterface
  36
  37         (*synthesize*)
  38         module mkUart_bs#(Clock core_clock, Reset core_reset)(Ifc_Uart_bs);
  39
  40                 Clock uart_clock<-exposeCurrentClock;
  41                 Reset uart_reset<-exposeCurrentReset;
  42                 Reg#(Bit#(16)) baud_value <-mkReg(`BAUD_RATE);
  43                 UART#(`Depth) uart <-mkUART(8,NONE,STOP_1,baud_value); // charasize,Parity,Stop Bits,BaudDIV
  44                 AXI4_Lite_Slave_Xactor_IFC #(`PADDR,`Reg_width,`USERSPACE)  s_xactor <- mkAXI4_Lite_Slave_Xactor(clocked_by core_clock, reset_by core_reset);
  45                 Reg#(Bit#(4)) rg_status <-mkReg(0);             //This register keeps track of whether some data
  46                                                                                                                         //is pending to be sent out through the UART Tx
  47
  48                 SyncFIFOIfc#(AXI4_Lite_Rd_Addr  #(`PADDR,`USERSPACE))           ff_rd_addr <-   mkSyncFIFOToCC(1,core_clock,core_reset);
  49                 SyncFIFOIfc#(AXI4_Lite_Wr_Addr  #(`PADDR, `USERSPACE))          ff_wr_addr <-   mkSyncFIFOToCC(1,core_clock,core_reset);
  50                 SyncFIFOIfc#(AXI4_Lite_Wr_Data  #(`Reg_width))                                  ff_wr_data <-   mkSyncFIFOToCC(1,core_clock,core_reset);
  51
  52                 SyncFIFOIfc#(AXI4_Lite_Rd_Data  #(`Reg_width,`USERSPACE))       ff_rd_resp <-   mkSyncFIFOFromCC(1,core_clock);
  53                 SyncFIFOIfc#(AXI4_Lite_Wr_Resp  #(`USERSPACE))                                  ff_wr_resp <-   mkSyncFIFOFromCC(1,core_clock);
  54
  55                 rule capture_read_request;
  56                         let req <- pop_o (s_xactor.o_rd_addr);
  57                         ff_rd_addr.enq(req);
  58                 endrule
  59
  60                 //Address 'h11304 is uart read data
  61                 rule rl_handle_axi4_uart_read(ff_rd_addr.notEmpty && ff_rd_addr.first.araddr[3:2]=='d1);
  62                         let req = ff_rd_addr.first;
  63                         ff_rd_addr.deq;
  64                         `ifdef verbose $display($time,"\tReq: RD_ADDR %h", req.araddr); `endif
  65                         Bit#(8) data<-uart.tx.get;
  66                         let lv_resp= AXI4_Lite_Rd_Data {rresp:AXI4_LITE_OKAY, rdata: zeroExtend(data), ruser: ?};
  67
  68                         `ifdef verbose $display($time,"\tResp: RD_RESP %h", req.araddr); `endif
  69                         ff_rd_resp.enq(lv_resp);
  70                 endrule
  71
  72                 //Address 'b11308 is uart read status
  73                 rule rl_handle_axi4_uart_status(ff_rd_addr.notEmpty && ff_rd_addr.first.araddr[3:2]!='d1);
  74                         let req =ff_rd_addr.first;
  75                         ff_rd_addr.deq;
  76                         `ifdef verbose $display($time,"\tReq: RD_ADDR %h", req.araddr); `endif
  77                         let lv_resp= AXI4_Lite_Rd_Data {rresp:AXI4_LITE_OKAY, rdata: zeroExtend(rg_status), ruser: ?};
  78                         if(req.araddr[3:2]==2)
  79                                 lv_resp.rdata=zeroExtend(rg_status);
  80                         else if(req.araddr[3:2]==3)
  81                                 lv_resp.rdata=zeroExtend(baud_value);
  82                         else
  83                                 lv_resp.rresp=AXI4_LITE_SLVERR;
  84
  85                         `ifdef verbose $display($time,"\tResp: RD_RESP %h Status: %b", req.araddr, rg_status); `endif
  86                         ff_rd_resp.enq(lv_resp);
  87                 endrule
  88
  89                 rule send_read_respone_to_bus;
  90                         s_xactor.i_rd_data.enq(ff_rd_resp.first);
  91                         ff_rd_resp.deq;
  92                 endrule
  93
  94                 rule capture_write_request;
  95                         let req <- pop_o (s_xactor.o_wr_addr);
  96                         let wr_data <- pop_o(s_xactor.o_wr_data);
  97                         ff_wr_addr.enq(req);
  98                         ff_wr_data.enq(wr_data);
  99                 endrule
 100
 101                 //Address 'b0000 is uart write data
 102                 rule rl_handle_axi4_write_rx(ff_wr_addr.notEmpty && ff_wr_data.notEmpty && ff_wr_addr.first.awaddr[3:2]==0);
 103                         let wr_addr = ff_wr_addr.first;
 104                         ff_wr_addr.deq;
 105                         let wr_data = ff_wr_data.first;
 106                         ff_wr_data.deq;
 107
 108                         `ifdef verbose $display($time,"\tReq: WR_ADDR %h", wr_addr.awaddr); `endif
 109                         `ifdef verbose $display($time,"\tReq: WR_DATA %h", wr_data.wdata); `endif
 110
 111                         uart.rx.put(truncate(wr_data.wdata));
 112          let lv_resp = AXI4_Lite_Wr_Resp {bresp: AXI4_LITE_OKAY, buser: ?};
 113         ff_wr_resp.enq(lv_resp);
 114                 endrule
 115
 116                 rule rl_handle_axi4_write(ff_wr_addr.notEmpty && ff_wr_data.notEmpty && ff_wr_addr.first.awaddr[3:2]!=0);
 117                         let wr_addr = ff_wr_addr.first;
 118                         ff_wr_addr.deq;
 119                         let wr_data = ff_wr_data.first;
 120                         ff_wr_data.deq;
 121
 122                         `ifdef verbose $display($time,"\tReq: WR_ADDR %h", wr_addr.awaddr); `endif
 123                         `ifdef verbose $display($time,"\tReq: WR_DATA %h", wr_data.wdata); `endif
 124
 125                         if(wr_addr.awaddr[3:2]=='d3) begin // change the baud value
 126                                 baud_value<=truncate(wr_data.wdata);
 127                         let lv_resp = AXI4_Lite_Wr_Resp {bresp: AXI4_LITE_OKAY, buser: ?};
 128                         ff_wr_resp.enq(lv_resp);
 129                         end
 130                         else begin
 131                         let lv_resp = AXI4_Lite_Wr_Resp {bresp: AXI4_LITE_SLVERR, buser: ?};
 132                         ff_wr_resp.enq(lv_resp);
 133                         end
 134                 endrule
 135
 136                 rule send_write_response;
 137                 s_xactor.i_wr_resp.enq(ff_wr_resp.first);
 138                         ff_wr_resp.deq;
 139                 endrule
 140
 141                 //The status register is 1 if the transmission FIFO is empty
 142                 (*no_implicit_conditions, fire_when_enabled*)
 143                 rule rl_update_status_reg;
 144                         let lv_status= {pack(uart.receiver_not_empty), pack(uart.receiver_not_full), pack(uart.transmittor_not_empty), pack(uart.transmission_done)};
 145                         rg_status<= lv_status;
 146                         `ifdef verbose
 147                         if(lv_status==0)
 148                                 $display($time,"-------UART1 TX Fifo not empty");
 149                         `endif
 150                 endrule
 151
 152                 interface slave_axi_uart = s_xactor.axi_side;
 153                 interface coe_rs232= uart.rs232;
 154         endmodule
 155 endpackage
 156