src/uncore/axi4lite/AXI4_Lite_Types.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 // Copyright (c) 2017 Bluespec, Inc.  All Rights Reserved
  15
  16 package AXI4_Lite_Types;
  17
  18 // ================================================================
  19 // Facilities for ARM AXI4-Lite, consisting of 5 independent channels:
  20 //   Write Address, Write Data, Write Response, Read Address and Read Data
  21
  22 // Ref: ARM document:
  23 //    AMBA AXI and ACE Protocol Specification
  24 //    AXI3, AXI4, and AXI4-Lite
  25 //    ACE and ACE-Lite
  26 //    ARM IHI 0022E (ID022613)
  27 //    Issue E, 22 Feb 2013
  28
  29 // See export list below
  30
  31 // ================================================================
  32 // Exports
  33
  34 export
  35
  36 // RTL-level interfaces (signals/buses)
  37 AXI4_Lite_Master_IFC (..),
  38 AXI4_Lite_Slave_IFC (..),
  39
  40 // Dummy slave that accepts no requests and generates no response
  41 // Used for tying-off unused slave interfaces on fabrics.
  42 dummy_AXI4_Lite_Slave_ifc,
  43
  44 // Higher-level enums and structs for the 5 AXI4 channel payloads
  45 AXI4_Lite_Resp (..),
  46
  47 AXI4_Lite_Wr_Addr (..),
  48 AXI4_Lite_Wr_Data (..),
  49 AXI4_Lite_Wr_Resp (..),
  50 AXI4_Lite_Rd_Addr (..),
  51 AXI4_Lite_Rd_Data (..),
  52
  53 // Higher-level FIFO-like interfaces for the 5 AXI4 channels,
  54 AXI4_Lite_Master_Xactor_IFC (..),
  55 AXI4_Lite_Slave_Xactor_IFC (..),
  56
  57 // Transactors from RTL-level interfacecs to FIFO-like interfaces.
  58 mkAXI4_Lite_Master_Xactor,
  59 mkAXI4_Lite_Slave_Xactor;
  60
  61 // ================================================================
  62 // BSV library imports
  63
  64 import FIFOF       :: *;
  65 import Connectable :: *;
  66
  67 // ----------------
  68 // BSV additional libs
  69
  70 import Semi_FIFOF :: *;
  71
  72 // ****************************************************************
  73 // ****************************************************************
  74 // Section: RTL-level interfaces
  75 // ****************************************************************
  76 // ****************************************************************
  77
  78 // ================================================================
  79 // These are the signal-level interfaces for an AXI4-Lite master.
  80 // The (*..*) attributes ensure that when bsc compiles this to Verilog,
  81 // we get exactly the signals specified in the ARM spec.
  82
  83 interface AXI4_Lite_Master_IFC #(numeric type wd_addr,
  84                                  numeric type wd_data,
  85                                  numeric type wd_user);
  86    // Wr Addr channel
  87    (* always_ready, result="awvalid" *) method Bool           m_awvalid;                                // out
  88    (* always_ready, result="awaddr" *)  method Bit #(wd_addr) m_awaddr;                                 // out
  89    (* always_ready, result="awuser" *)  method Bit #(wd_user) m_awuser;                                 // out
  90    (* always_ready, result="awsize" *)  method Bit #(3)  m_awsize;                                                      // out
  91    (* always_ready, always_enabled *)   method Action m_awready ((* port="awready" *) Bool awready);    // in
  92
  93    // Wr Data channel
  94    (* always_ready, result="wvalid" *)  method Bool                      m_wvalid;                      // out
  95    (* always_ready, result="wdata" *)   method Bit #(wd_data)            m_wdata;                       // out
  96    (* always_ready, result="wstrb" *)   method Bit #(TDiv #(wd_data, 8)) m_wstrb;                       // out
  97    (* always_ready, always_enabled *)   method Action m_wready ((* port="wready" *)  Bool wready);      // in
  98
  99    // Wr Response channel
 100    (* always_ready, always_enabled *)
 101    method Action m_bvalid ((* port="bvalid" *)  Bool           bvalid,    // in
 102                            (* port="bresp"  *)  Bit #(2)       bresp,     // in
 103                            (* port="buser"  *)  Bit #(wd_user) buser);    // in
 104    (* always_ready, result="bready" *)
 105    method Bool m_bready;                                            // out
 106
 107    // Rd Addr channel
 108    (* always_ready, result="arvalid" *) method Bool            m_arvalid;                               // out
 109    (* always_ready, result="araddr" *)  method Bit #(wd_addr)  m_araddr;                                // out
 110    (* always_ready, result="aruser" *)  method Bit #(wd_user)  m_aruser;                                // out
 111    (* always_ready, result="arsize" *)  method Bit #(3)  m_arsize;                                                      // out
 112    (* always_ready, always_enabled  *)  method Action m_arready ((* port="arready" *) Bool arready);    // in
 113
 114    // Rd Data channel
 115    (* always_ready, always_enabled  *)
 116    method Action m_rvalid ((* port="rvalid" *) Bool           rvalid,    // in
 117                            (* port="rresp" *)  Bit #(2)       rresp,     // in
 118                            (* port="rdata" *)  Bit #(wd_data) rdata,     // in
 119                            (* port="ruser" *)  Bit #(wd_user) ruser);    // in
 120    (* always_ready, result="rready" *)
 121    method Bool m_rready;                                                 // out
 122 endinterface: AXI4_Lite_Master_IFC
 123
 124 // ================================================================
 125 // These are the signal-level interfaces for an AXI4-Lite slave.
 126 // The (*..*) attributes ensure that when bsc compiles this to Verilog,
 127 // we get exactly the signals specified in the ARM spec.
 128
 129 interface AXI4_Lite_Slave_IFC #(numeric type wd_addr,
 130                                 numeric type wd_data,
 131                                 numeric type wd_user);
 132    // Wr Addr channel
 133    (* always_ready, always_enabled *)
 134    method Action m_awvalid ((* port="awvalid" *) Bool           awvalid,    // in
 135                             (* port="awaddr" *)  Bit #(wd_addr) awaddr,     // in
 136                             (* port="awsize" *)   Bit #(3) awsize,                                              // in
 137                             (* port="awuser" *)  Bit #(wd_user) awuser);    // in
 138    (* always_ready, result="awready" *)
 139    method Bool m_awready;                                                   // out
 140
 141    // Wr Data channel
 142    (* always_ready, always_enabled *)
 143    method Action m_wvalid ((* port="wvalid" *) Bool                     wvalid,    // in
 144                            (* port="wdata" *)  Bit #(wd_data)           wdata,     // in
 145                            (* port="wstrb" *)  Bit #(TDiv #(wd_data,8)) wstrb);    // in
 146    (* always_ready, result="wready" *)
 147    method Bool m_wready;                                                           // out
 148
 149    // Wr Response channel
 150    (* always_ready, result="bvalid" *)  method Bool           m_bvalid;                                 // out
 151    (* always_ready, result="bresp" *)   method Bit #(2)       m_bresp;                                  // out
 152    (* always_ready, result="buser" *)   method Bit #(wd_user) m_buser;                                  // out
 153    (* always_ready, always_enabled *)   method Action m_bready  ((* port="bready" *)   Bool bready);    // in
 154
 155    // Rd Addr channel
 156    (* always_ready, always_enabled *)
 157    method Action m_arvalid ((* port="arvalid" *) Bool           arvalid,    // in
 158                             (* port="araddr" *)  Bit #(wd_addr) araddr,     // in
 159                                  (* port="arsize" *)     Bit #(3)  arsize,        // in
 160                             (* port="aruser" *)  Bit #(wd_user) aruser);    // in
 161    (* always_ready, result="arready" *)
 162    method Bool m_arready;                                                   // out
 163
 164    // Rd Data channel
 165    (* always_ready, result="rvalid" *)  method Bool           m_rvalid;                                 // out
 166    (* always_ready, result="rresp" *)   method Bit #(2)       m_rresp;                                  // out
 167    (* always_ready, result="rdata" *)   method Bit #(wd_data) m_rdata;                                  // out
 168    (* always_ready, result="ruser" *)   method Bit #(wd_user) m_ruser;                                  // out
 169    (* always_ready, always_enabled *)   method Action m_rready  ((* port="rready" *)   Bool rready);    // in
 170 endinterface: AXI4_Lite_Slave_IFC
 171
 172 // ================================================================
 173 // Connecting signal-level interfaces
 174
 175 instance Connectable #(AXI4_Lite_Master_IFC #(wd_addr, wd_data, wd_user),
 176                        AXI4_Lite_Slave_IFC  #(wd_addr, wd_data, wd_user));
 177
 178    module mkConnection #(AXI4_Lite_Master_IFC #(wd_addr, wd_data, wd_user) axim,
 179                          AXI4_Lite_Slave_IFC  #(wd_addr, wd_data, wd_user) axis)
 180                        (Empty);
 181
 182       (* fire_when_enabled, no_implicit_conditions *)
 183       rule rl_wr_addr_channel;
 184          axis.m_awvalid (axim.m_awvalid, axim.m_awaddr, axim.m_awsize, axim.m_awuser);
 185          axim.m_awready (axis.m_awready);
 186       endrule
 187
 188       (* fire_when_enabled, no_implicit_conditions *)
 189       rule rl_wr_data_channel;
 190          axis.m_wvalid (axim.m_wvalid, axim.m_wdata, axim.m_wstrb);
 191          axim.m_wready (axis.m_wready);
 192       endrule
 193
 194       (* fire_when_enabled, no_implicit_conditions *)
 195       rule rl_wr_response_channel;
 196          axim.m_bvalid (axis.m_bvalid, axis.m_bresp, axis.m_buser);
 197          axis.m_bready (axim.m_bready);
 198       endrule
 199
 200       (* fire_when_enabled, no_implicit_conditions *)
 201       rule rl_rd_addr_channel;
 202          axis.m_arvalid (axim.m_arvalid, axim.m_araddr, axim.m_arsize, axim.m_aruser);
 203          axim.m_arready (axis.m_arready);
 204       endrule
 205
 206       (* fire_when_enabled, no_implicit_conditions *)
 207       rule rl_rd_data_channel;
 208          axim.m_rvalid (axis.m_rvalid, axis.m_rresp, axis.m_rdata, axis.m_ruser);
 209          axis.m_rready (axim.m_rready);
 210       endrule
 211    endmodule
 212 endinstance
 213
 214 // ================================================================
 215 // AXI4-Lite dummy slave: never accepts requests, never produces responses
 216
 217 AXI4_Lite_Slave_IFC #(wd_addr, wd_data, wd_user)
 218    dummy_AXI4_Lite_Slave_ifc = interface AXI4_Lite_Slave_IFC
 219                                   // Wr Addr channel
 220                                   method Action m_awvalid (Bool           awvalid,
 221                                                            Bit #(wd_addr) awaddr,
 222                                                                 Bit #(3)                        awsize,
 223                                                            Bit #(wd_user) awuser);
 224                                      noAction;
 225                                   endmethod
 226
 227                                   method Bool m_awready;
 228                                      return False;
 229                                   endmethod
 230
 231                                   // Wr Data channel
 232                                   method Action m_wvalid (Bool                     wvalid,
 233                                                           Bit #(wd_data)           wdata,
 234                                                           Bit #(TDiv #(wd_data,8)) wstrb);
 235                                      noAction;
 236                                   endmethod
 237
 238                                   method Bool m_wready;
 239                                      return False;
 240                                   endmethod
 241
 242                                   // Wr Response channel
 243                                   method Bool m_bvalid;
 244                                      return False;
 245                                   endmethod
 246
 247                                   method Bit #(2) m_bresp;
 248                                      return 0;
 249                                   endmethod
 250
 251                                   method Bit #(wd_user) m_buser;
 252                                      return ?;
 253                                   endmethod
 254
 255                                   method Action m_bready  (Bool bready);
 256                                      noAction;
 257                                   endmethod
 258
 259                                   // Rd Addr channel
 260                                   method Action m_arvalid (Bool           arvalid,
 261                                                            Bit #(wd_addr) araddr,
 262                                                                 Bit#(3)                          arsize,
 263                                                            Bit #(wd_user) aruser);
 264                                      noAction;
 265                                   endmethod
 266
 267                                   method Bool m_arready;
 268                                      return False;
 269                                   endmethod
 270
 271                                   // Rd Data channel
 272                                   method Bool m_rvalid;
 273                                      return False;
 274                                   endmethod
 275
 276                                   method Bit #(2) m_rresp;
 277                                      return 0;
 278                                   endmethod
 279
 280                                   method Bit #(wd_data) m_rdata;
 281                                      return 0;
 282                                   endmethod
 283
 284                                   method Bit #(wd_user) m_ruser;
 285                                      return ?;
 286                                   endmethod
 287
 288                                   method Action m_rready  (Bool rready);
 289                                      noAction;
 290                                   endmethod
 291                                endinterface;
 292
 293 // ****************************************************************
 294 // ****************************************************************
 295 // Section: Higher-level FIFO-like interfaces and transactors
 296 // ****************************************************************
 297 // ****************************************************************
 298
 299 // ================================================================
 300 // Higher-level types for payloads (rather than just bits)
 301
 302 typedef enum { AXI4_LITE_OKAY, AXI4_LITE_EXOKAY, AXI4_LITE_SLVERR, AXI4_LITE_DECERR } AXI4_Lite_Resp
 303 deriving (Bits, Eq, FShow);
 304
 305 // Write Address channel
 306
 307 typedef struct {
 308    Bit #(wd_addr)  awaddr;
 309    Bit #(wd_user)  awuser;
 310         Bit#(3)                                 awsize;
 311    } AXI4_Lite_Wr_Addr #(numeric type wd_addr, numeric type wd_user)
 312 deriving (Bits, FShow);
 313
 314 // Write Data channel
 315
 316 typedef struct {
 317    Bit #(wd_data)             wdata;
 318    Bit #(TDiv #(wd_data, 8))  wstrb;
 319    } AXI4_Lite_Wr_Data #(numeric type wd_data)
 320 deriving (Bits, FShow);
 321
 322 // Write Response channel
 323
 324 typedef struct {
 325    AXI4_Lite_Resp  bresp;
 326    Bit #(wd_user)  buser;
 327    } AXI4_Lite_Wr_Resp #(numeric type wd_user)
 328 deriving (Bits, FShow);
 329
 330 // Read Address channel
 331
 332 typedef struct {
 333    Bit #(wd_addr)  araddr;
 334    Bit #(wd_user)  aruser;
 335         Bit#(3)                  arsize;
 336    } AXI4_Lite_Rd_Addr #(numeric type wd_addr, numeric type wd_user)
 337 deriving (Bits, FShow);
 338
 339 // Read Data channel
 340
 341 typedef struct {
 342    AXI4_Lite_Resp  rresp;
 343    Bit #(wd_data)  rdata;
 344    Bit #(wd_user)  ruser;
 345    } AXI4_Lite_Rd_Data #(numeric type wd_data, numeric type wd_user)
 346 deriving (Bits, FShow);
 347
 348 // ================================================================
 349 // Master transactor interface
 350
 351 interface AXI4_Lite_Master_Xactor_IFC #(numeric type wd_addr,
 352                                         numeric type wd_data,
 353                                         numeric type wd_user);
 354    method Action reset;
 355
 356    // AXI side
 357    interface AXI4_Lite_Master_IFC #(wd_addr, wd_data, wd_user) axi_side;
 358
 359    // FIFOF side
 360    interface FIFOF_I #(AXI4_Lite_Wr_Addr #(wd_addr, wd_user)) i_wr_addr;
 361    interface FIFOF_I #(AXI4_Lite_Wr_Data #(wd_data))          i_wr_data;
 362    interface FIFOF_O #(AXI4_Lite_Wr_Resp #(wd_user))          o_wr_resp;
 363
 364    interface FIFOF_I #(AXI4_Lite_Rd_Addr #(wd_addr, wd_user)) i_rd_addr;
 365    interface FIFOF_O #(AXI4_Lite_Rd_Data #(wd_data, wd_user)) o_rd_data;
 366 endinterface: AXI4_Lite_Master_Xactor_IFC
 367
 368 // ----------------------------------------------------------------
 369 // Master transactor
 370
 371 module mkAXI4_Lite_Master_Xactor (AXI4_Lite_Master_Xactor_IFC #(wd_addr, wd_data, wd_user));
 372
 373    Bool unguarded = True;
 374    Bool guarded   = False;
 375
 376    // These FIFOs are guarded on BSV side, unguarded on AXI side
 377    FIFOF #(AXI4_Lite_Wr_Addr #(wd_addr, wd_user)) f_wr_addr <- mkGFIFOF (guarded, unguarded);
 378    FIFOF #(AXI4_Lite_Wr_Data #(wd_data))          f_wr_data <- mkGFIFOF (guarded, unguarded);
 379    FIFOF #(AXI4_Lite_Wr_Resp #(wd_user))          f_wr_resp <- mkGFIFOF (unguarded, guarded);
 380
 381    FIFOF #(AXI4_Lite_Rd_Addr #(wd_addr, wd_user))  f_rd_addr <- mkGFIFOF (guarded, unguarded);
 382    FIFOF #(AXI4_Lite_Rd_Data #(wd_data, wd_user)) f_rd_data  <- mkGFIFOF (unguarded, guarded);
 383
 384    // ----------------------------------------------------------------
 385    // INTERFACE
 386
 387    method Action reset;
 388       f_wr_addr.clear;
 389       f_wr_data.clear;
 390       f_wr_resp.clear;
 391       f_rd_addr.clear;
 392       f_rd_data.clear;
 393    endmethod
 394
 395    // AXI side
 396    interface axi_side = interface AXI4_Lite_Master_IFC;
 397                            // Wr Addr channel
 398                            method Bool           m_awvalid = f_wr_addr.notEmpty;
 399                            method Bit #(wd_addr) m_awaddr  = f_wr_addr.first.awaddr;
 400                            method Bit #(wd_user) m_awuser  = f_wr_addr.first.awuser;
 401                                 method Bit #(3)          m_awsize  = f_wr_addr.first.awsize;
 402                            method Action m_awready (Bool awready);
 403                               if (f_wr_addr.notEmpty && awready) f_wr_addr.deq;
 404                            endmethod
 405
 406                            // Wr Data channel
 407                            method Bool                       m_wvalid = f_wr_data.notEmpty;
 408                            method Bit #(wd_data)             m_wdata  = f_wr_data.first.wdata;
 409                            method Bit #(TDiv #(wd_data, 8))  m_wstrb  = f_wr_data.first.wstrb;
 410                            method Action m_wready (Bool wready);
 411                               if (f_wr_data.notEmpty && wready) f_wr_data.deq;
 412                            endmethod
 413
 414                            // Wr Response channel
 415                            method Action m_bvalid (Bool bvalid, Bit #(2) bresp, Bit #(wd_user) buser);
 416                               if (bvalid && f_wr_resp.notFull)
 417                                  f_wr_resp.enq (AXI4_Lite_Wr_Resp {bresp: unpack (bresp), buser: buser});
 418                            endmethod
 419
 420                            method Bool m_bready;
 421                               return f_wr_resp.notFull;
 422                            endmethod
 423
 424                            // Rd Addr channel
 425                            method Bool           m_arvalid = f_rd_addr.notEmpty;
 426                            method Bit #(wd_addr) m_araddr  = f_rd_addr.first.araddr;
 427                            method Bit #(wd_user) m_aruser  = f_rd_addr.first.aruser;
 428                                 method Bit #(3)          m_arsize        = f_rd_addr.first.arsize;
 429                            method Action m_arready (Bool arready);
 430                               if (f_rd_addr.notEmpty && arready) f_rd_addr.deq;
 431                            endmethod
 432
 433                            // Rd Data channel
 434                            method Action m_rvalid (Bool           rvalid,
 435                                                    Bit #(2)       rresp,
 436                                                    Bit #(wd_data) rdata,
 437                                                    Bit #(wd_user) ruser);
 438                               if (rvalid && f_rd_data.notFull)
 439                                  f_rd_data.enq (AXI4_Lite_Rd_Data {rresp: unpack (rresp),
 440                                                                    rdata: rdata,
 441                                                                    ruser: ruser});
 442                            endmethod
 443
 444                            method Bool m_rready;
 445                               return f_rd_data.notFull;
 446                            endmethod
 447
 448                         endinterface;
 449
 450    // FIFOF side
 451    interface i_wr_addr = to_FIFOF_I (f_wr_addr);
 452    interface i_wr_data = to_FIFOF_I (f_wr_data);
 453    interface o_wr_resp = to_FIFOF_O (f_wr_resp);
 454
 455    interface i_rd_addr = to_FIFOF_I (f_rd_addr);
 456    interface o_rd_data = to_FIFOF_O (f_rd_data);
 457 endmodule: mkAXI4_Lite_Master_Xactor
 458
 459 // ================================================================
 460 // Slave transactor interface
 461
 462 interface AXI4_Lite_Slave_Xactor_IFC #(numeric type wd_addr,
 463                                        numeric type wd_data,
 464                                        numeric type wd_user);
 465    method Action reset;
 466
 467    // AXI side
 468    interface AXI4_Lite_Slave_IFC #(wd_addr, wd_data, wd_user) axi_side;
 469
 470    // FIFOF side
 471    interface FIFOF_O #(AXI4_Lite_Wr_Addr #(wd_addr, wd_user)) o_wr_addr;
 472    interface FIFOF_O #(AXI4_Lite_Wr_Data #(wd_data))          o_wr_data;
 473    interface FIFOF_I #(AXI4_Lite_Wr_Resp #(wd_user))          i_wr_resp;
 474
 475    interface FIFOF_O #(AXI4_Lite_Rd_Addr #(wd_addr, wd_user)) o_rd_addr;
 476    interface FIFOF_I #(AXI4_Lite_Rd_Data #(wd_data, wd_user)) i_rd_data;
 477 endinterface: AXI4_Lite_Slave_Xactor_IFC
 478
 479 // ----------------------------------------------------------------
 480 // Slave transactor
 481
 482 module mkAXI4_Lite_Slave_Xactor (AXI4_Lite_Slave_Xactor_IFC #(wd_addr, wd_data, wd_user));
 483
 484    Bool unguarded = True;
 485    Bool guarded   = False;
 486
 487    // These FIFOs are guarded on BSV side, unguarded on AXI side
 488    FIFOF #(AXI4_Lite_Wr_Addr #(wd_addr, wd_user)) f_wr_addr <- mkGFIFOF (unguarded, guarded);
 489    FIFOF #(AXI4_Lite_Wr_Data #(wd_data))          f_wr_data <- mkGFIFOF (unguarded, guarded);
 490    FIFOF #(AXI4_Lite_Wr_Resp #(wd_user))          f_wr_resp <- mkGFIFOF (guarded, unguarded);
 491
 492    FIFOF #(AXI4_Lite_Rd_Addr #(wd_addr, wd_user)) f_rd_addr <- mkGFIFOF (unguarded, guarded);
 493    FIFOF #(AXI4_Lite_Rd_Data #(wd_data, wd_user)) f_rd_data <- mkGFIFOF (guarded, unguarded);
 494
 495    // ----------------------------------------------------------------
 496    // INTERFACE
 497
 498    method Action reset;
 499       f_wr_addr.clear;
 500       f_wr_data.clear;
 501       f_wr_resp.clear;
 502       f_rd_addr.clear;
 503       f_rd_data.clear;
 504    endmethod
 505
 506    // AXI side
 507    interface axi_side = interface AXI4_Lite_Slave_IFC;
 508                            // Wr Addr channel
 509                            method Action m_awvalid (Bool           awvalid,
 510                                                     Bit #(wd_addr) awaddr,
 511                                                          Bit#(3) awsize,
 512                                                     Bit #(wd_user) awuser);
 513                               if (awvalid && f_wr_addr.notFull)
 514                                  f_wr_addr.enq (AXI4_Lite_Wr_Addr {awaddr: awaddr,
 515                                                                         awsize:awsize,
 516                                                                    awuser: awuser});
 517                            endmethod
 518
 519                            method Bool m_awready;
 520                               return f_wr_addr.notFull;
 521                            endmethod
 522
 523                            // Wr Data channel
 524                            method Action m_wvalid (Bool                      wvalid,
 525                                                    Bit #(wd_data)            wdata,
 526                                                    Bit #(TDiv #(wd_data, 8)) wstrb);
 527                               if (wvalid && f_wr_data.notFull)
 528                                  f_wr_data.enq (AXI4_Lite_Wr_Data {wdata: wdata, wstrb: wstrb});
 529                            endmethod
 530
 531                            method Bool m_wready;
 532                               return f_wr_data.notFull;
 533                            endmethod
 534
 535                            // Wr Response channel
 536                            method Bool           m_bvalid = f_wr_resp.notEmpty;
 537                            method Bit #(2)       m_bresp  = pack (f_wr_resp.first.bresp);
 538                            method Bit #(wd_user) m_buser  = f_wr_resp.first.buser;
 539                            method Action m_bready (Bool bready);
 540                               if (bready && f_wr_resp.notEmpty)
 541                                  f_wr_resp.deq;
 542                            endmethod
 543
 544                            // Rd Addr channel
 545                            method Action m_arvalid (Bool           arvalid,
 546                                                     Bit #(wd_addr) araddr,
 547                                                          Bit#(3)                                 arsize,
 548                                                     Bit #(wd_user) aruser);
 549                               if (arvalid && f_rd_addr.notFull)
 550                                  f_rd_addr.enq (AXI4_Lite_Rd_Addr {araddr: araddr,
 551                                                                         arsize: arsize,
 552                                                                    aruser: aruser});
 553                            endmethod
 554
 555                            method Bool m_arready;
 556                               return f_rd_addr.notFull;
 557                            endmethod
 558
 559                            // Rd Data channel
 560                            method Bool           m_rvalid = f_rd_data.notEmpty;
 561                            method Bit #(2)       m_rresp  = pack (f_rd_data.first.rresp);
 562                            method Bit #(wd_data) m_rdata  = f_rd_data.first.rdata;
 563                            method Bit #(wd_user) m_ruser  = f_rd_data.first.ruser;
 564                            method Action m_rready (Bool rready);
 565                               if (rready && f_rd_data.notEmpty)
 566                                  f_rd_data.deq;
 567                            endmethod
 568                         endinterface;
 569
 570    // FIFOF side
 571    interface o_wr_addr = to_FIFOF_O (f_wr_addr);
 572    interface o_wr_data = to_FIFOF_O (f_wr_data);
 573    interface i_wr_resp = to_FIFOF_I (f_wr_resp);
 574
 575    interface o_rd_addr = to_FIFOF_O (f_rd_addr);
 576    interface i_rd_data = to_FIFOF_I (f_rd_data);
 577 endmodule: mkAXI4_Lite_Slave_Xactor
 578
 579 // ================================================================
 580
 581 endpackage