tidy up flexbus interface
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 27 Jul 2018 05:51:12 +0000 (06:51 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 27 Jul 2018 05:51:12 +0000 (06:51 +0100)
src/peripherals/flexbus/FlexBus_Types.bsv
src/peripherals/rgbttl/Makefile
src/peripherals/rgbttl/instance_defines.bsv [deleted file]
src/peripherals/rgbttl/test/instance_defines.bsv [new file with mode: 0644]

index a21ccf5e6aef5c49179284700dabb07776cacbf4..9e3533e40df248ba780b3f1c95597a4d7451ba98 100644 (file)
@@ -67,19 +67,19 @@ interface FlexBus_Master_IFC;
    // FlexBus External Signals
   
    // AD inout bus separate for now in BSV
-   interface Get#(Bit#(32))  m_AD;         // out
-   interface Put#(Bit#(32)) m_din;         // in
+   interface Get#(Bit#(32)) AD;      // out
+   interface Put#(Bit#(32)) din;     // in
 
-   interface Get#(Bit#(1))   m_R_Wn;       // out
-   interface Get#(Bit#(2))   m_TSIZ;       // out
+   interface Get#(Bit#(1))  R_Wn;    // out
+   interface Get#(Bit#(2))  TSIZ;    // out
 
-   interface Get#(Bit#(6))   m_FBCSn;      // out
-   interface Get#(Bit#(4))   m_BE_BWEn;    // out
-   interface Get#(Bit#(1))   m_TBSTn;      // out
-   interface Get#(Bit#(1))   m_OEn;        // out
+   interface Get#(Bit#(6))  FBCSn;   // out
+   interface Get#(Bit#(4))  BWEn; // out
+   interface Get#(Bit#(1))  TBSTn;   // out
+   interface Get#(Bit#(1))  OEn;     // out
 
-   interface Get#(Bit#(1))   m_ALE;        // out
-   interface Put#(Bit#(1))   tAn;          // in
+   interface Get#(Bit#(1))  ALE;     // out
+   interface Put#(Bit#(1))  tAn;     // in
 
 endinterface: FlexBus_Master_IFC
 
@@ -1079,55 +1079,55 @@ interface flexbus_side = interface FlexBus_Master_IFC;
         endmethod
     endinterface;
 
-    interface m_din = interface Put
+    interface din = interface Put
         method Action put(Bit#(32) in) if(c_din[0] matches tagged Invalid);
             c_din[0] <= tagged Valid in;
         endmethod
     endinterface;
 
-    interface m_AD = interface Get
+    interface AD = interface Get
         method ActionValue#(Bit#(32)) get;
             return r_AD;
         endmethod
     endinterface;
 
-    interface m_R_Wn = interface Get
+    interface R_Wn = interface Get
         method ActionValue#(Bit#(1)) get;
             return r_R_Wn;
         endmethod
     endinterface;
 
-    interface m_TSIZ = interface Get
+    interface TSIZ = interface Get
         method ActionValue#(Bit#(2)) get;
             return r_TSIZ;
         endmethod
     endinterface;
 
-    interface m_FBCSn = interface Get
+    interface FBCSn = interface Get
         method ActionValue#(Bit#(6)) get;
             return r_FBCSn;
         endmethod
     endinterface;
 
-    interface m_BE_BWEn = interface Get
+    interface BWEn = interface Get
         method ActionValue#(Bit#(4)) get;
             return r_BE_BWEn;
         endmethod
     endinterface;
 
-    interface m_TBSTn = interface Get
+    interface TBSTn = interface Get
         method ActionValue#(Bit#(1)) get;
             return r_TBSTn;
         endmethod
     endinterface;
 
-    interface m_OEn = interface Get
+    interface OEn = interface Get
         method ActionValue#(Bit#(1)) get;
             return r_OEn;
         endmethod
     endinterface;
 
-    interface m_ALE = interface Get
+    interface ALE = interface Get
         method ActionValue#(Bit#(1)) get;
             return r_ALE;
         endmethod
index d1122695890e4eeada60e682cd0876b506d287c2..21c08371494fddb6cdfa09b6ad4bed57d921128f 100644 (file)
@@ -6,18 +6,9 @@ TOP_DIR:=./
 WORKING_DIR := $(shell pwd)
 
 BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC:./bsv_lib/
-BSVINCDIR:= $(BSVINCDIR):../../../src/uncore/axi4
-BSVINCDIR:= $(BSVINCDIR):../../../src/uncore/axi4lite
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/gpio
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/rgbttl
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/i2c
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/mux
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/plic
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/pwm
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/qspi
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/spi
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/sdmmc
-BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/uart
+BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4
+BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4lite
+BSVINCDIR:= $(BSVINCDIR):./test
 
 default: gen_verilog
 
diff --git a/src/peripherals/rgbttl/instance_defines.bsv b/src/peripherals/rgbttl/instance_defines.bsv
deleted file mode 100644 (file)
index 38780f5..0000000
+++ /dev/null
@@ -1,24 +0,0 @@
-`define ADDR 32
-`define PADDR 32
-`define DATA 64
-`define Reg_width 64
-`define USERSPACE 0
-
-// TODO: work out if these are needed
-`define PWM_AXI4Lite
-`define PRFDEPTH 6
-`define VADDR 39
-`define DCACHE_BLOCK_SIZE 4
-`define DCACHE_WORD_SIZE 8
-`define PERFMONITORS                            64
-`define DCACHE_WAYS 4
-`define DCACHE_TAG_BITS 20      // tag_bits = 52
-`define PLIC
-       `define PLICBase                'h0c000000
-       `define PLICEnd         'h10000000
-`define INTERRUPT_PINS 64
-
-`define BAUD_RATE 130
-`ifdef simulate
-  `define BAUD_RATE 5 //130 //
-`endif
diff --git a/src/peripherals/rgbttl/test/instance_defines.bsv b/src/peripherals/rgbttl/test/instance_defines.bsv
new file mode 100644 (file)
index 0000000..38780f5
--- /dev/null
@@ -0,0 +1,24 @@
+`define ADDR 32
+`define PADDR 32
+`define DATA 64
+`define Reg_width 64
+`define USERSPACE 0
+
+// TODO: work out if these are needed
+`define PWM_AXI4Lite
+`define PRFDEPTH 6
+`define VADDR 39
+`define DCACHE_BLOCK_SIZE 4
+`define DCACHE_WORD_SIZE 8
+`define PERFMONITORS                            64
+`define DCACHE_WAYS 4
+`define DCACHE_TAG_BITS 20      // tag_bits = 52
+`define PLIC
+       `define PLICBase                'h0c000000
+       `define PLICEnd         'h10000000
+`define INTERRUPT_PINS 64
+
+`define BAUD_RATE 130
+`ifdef simulate
+  `define BAUD_RATE 5 //130 //
+`endif