Merge pull request #4 from sifive/periphery-keys
[sifive-blocks.git] / src / main / scala / devices / gpio / GPIOPeriphery.scala
1 // See LICENSE for license details.
2 package sifive.blocks.devices.gpio
3
4 import Chisel._
5 import config.Field
6 import diplomacy.LazyModule
7 import rocketchip.{
8 HasTopLevelNetworks,
9 HasTopLevelNetworksBundle,
10 HasTopLevelNetworksModule
11 }
12 import uncore.tilelink2.TLFragmenter
13
14 case object PeripheryGPIOKey extends Field[GPIOParams]
15
16 trait HasPeripheryGPIO extends HasTopLevelNetworks {
17 val gpioParams = p(PeripheryGPIOKey)
18 val gpio = LazyModule(new TLGPIO(peripheryBusBytes, gpioParams))
19 gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
20 intBus.intnode := gpio.intnode
21 }
22
23 trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle {
24 val outer: HasPeripheryGPIO
25 val gpio = new GPIOPortIO(outer.gpioParams)
26 }
27
28 trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule {
29 val outer: HasPeripheryGPIO
30 val io: HasPeripheryGPIOBundle
31 io.gpio <> outer.gpio.module.io.port
32 }