src/main/scala/devices/i2c/I2CPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.i2c
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Field
   6 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
   7 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
   8
   9 case object PeripheryI2CKey extends Field[Seq[I2CParams]]
  10
  11 trait HasPeripheryI2C extends HasPeripheryBus {
  12   val i2cParams = p(PeripheryI2CKey)
  13   val i2c = i2cParams map { params =>
  14     val i2c = LazyModule(new TLI2C(pbus.beatBytes, params))
  15     i2c.node := pbus.toVariableWidthSlaves
  16     ibus.fromSync := i2c.intnode
  17     i2c
  18   }
  19 }
  20
  21 trait HasPeripheryI2CBundle {
  22   val i2cs: Vec[I2CPort]
  23
  24   def I2CtoGPIOPins(syncStages: Int = 0): Seq[I2CPinsIO] = i2cs.map { i =>
  25     val pins = Module(new I2CGPIOPort(syncStages))
  26     pins.io.i2c <> i
  27     pins.io.pins
  28   }
  29 }
  30
  31 trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle {
  32   val outer: HasPeripheryI2C
  33   val i2cs = IO(Vec(outer.i2cParams.size, new I2CPort))
  34
  35   (i2cs zip outer.i2c).foreach { case (io, device) =>
  36     io <> device.module.io.port
  37   }
  38 }