Initial (compilable) version of I2C (no actual logic yet)
[sifive-blocks.git] / src / main / scala / devices / i2c / I2CPeriphery.scala
1 // See LICENSE for license details.
2 package sifive.blocks.devices.i2c
3
4 import Chisel._
5 import diplomacy.LazyModule
6 import rocketchip.{TopNetwork,TopNetworkModule}
7 import uncore.tilelink2.TLFragmenter
8
9 trait PeripheryI2C {
10 this: TopNetwork { val i2cConfigs: Seq[I2CConfig] } =>
11 val i2cDevices = i2cConfigs.zipWithIndex.map { case (c, i) =>
12 val i2c = LazyModule(new TLI2C(c))
13 i2c.suggestName(s"i2c$i")
14 i2c.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
15 intBus.intnode := i2c.intnode
16 i2c
17 }
18 }
19
20 trait PeripheryI2CBundle {
21 this: { val i2cConfigs: Seq[I2CConfig] } =>
22 val i2cs = Vec(i2cConfigs.size, new I2CPort)
23 }
24
25 trait PeripheryI2CModule {
26 this: TopNetworkModule {
27 val i2cConfigs: Seq[I2CConfig]
28 val outer: PeripheryI2C
29 val io: PeripheryI2CBundle
30 } =>
31 (io.i2cs zip outer.i2cDevices).foreach { case (io, device) =>
32 io <> device.module.io.port
33 }
34 }