src/main/scala/devices/mockaon/MockAON.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.mockaon
   3
   4 import Chisel._
   5 import config._
   6 import regmapper._
   7 import uncore.tilelink2._
   8
   9 import sifive.blocks.util.GenericTimer
  10
  11 case class MockAONParams(
  12     address: BigInt = BigInt(0x10000000),
  13     nBackupRegs: Int = 16) {
  14   def size: Int = 0x1000
  15   def regBytes: Int = 4
  16   def wdogOffset: Int = 0
  17   def rtcOffset: Int = 0x40
  18   def backupRegOffset: Int = 0x80
  19   def pmuOffset: Int = 0x100
  20 }
  21
  22 class MockAONPMUIO extends Bundle {
  23   val vddpaden = Bool(OUTPUT)
  24   val dwakeup = Bool(INPUT)
  25 }
  26
  27 class MockAONMOffRstIO extends Bundle {
  28   val hfclkrst = Bool(OUTPUT)
  29   val corerst = Bool(OUTPUT)
  30 }
  31
  32 trait HasMockAONBundleContents extends Bundle {
  33
  34   // Output of the Power Management Sequencer
  35   val moff = new MockAONMOffRstIO
  36
  37   // This goes out to wrapper
  38   // to be combined to create aon_rst.
  39   val wdog_rst = Bool(OUTPUT)
  40
  41   // This goes out to wrapper
  42   // and comes back as our clk
  43   val lfclk = Clock(OUTPUT)
  44
  45   val pmu = new MockAONPMUIO
  46
  47   val lfextclk = Clock(INPUT)
  48
  49   val resetCauses = new ResetCauses().asInput
  50 }
  51
  52 trait HasMockAONModuleContents extends Module with HasRegMap {
  53   val io: HasMockAONBundleContents
  54   val params: MockAONParams
  55   val c = params
  56
  57   // the expectation here is that Chisel's implicit reset is aonrst,
  58   // which is asynchronous, so don't use synchronous-reset registers.
  59
  60   val rtc = Module(new RTC)
  61
  62   val pmu = Module(new PMU(new DevKitPMUConfig))
  63   io.moff <> pmu.io.control
  64   io.pmu.vddpaden := pmu.io.control.vddpaden
  65   pmu.io.wakeup.dwakeup := io.pmu.dwakeup
  66   pmu.io.wakeup.awakeup := Bool(false)
  67   pmu.io.wakeup.rtc := rtc.io.ip(0)
  68   pmu.io.resetCauses := io.resetCauses
  69   val pmuRegMap = {
  70     val regs = pmu.io.regs.wakeupProgram ++ pmu.io.regs.sleepProgram ++
  71       Seq(pmu.io.regs.ie, pmu.io.regs.cause, pmu.io.regs.sleep, pmu.io.regs.key)
  72     for ((r, i) <- regs.zipWithIndex)
  73       yield (c.pmuOffset + c.regBytes*i) -> Seq(r.toRegField())
  74   }
  75   interrupts(1) := rtc.io.ip(0)
  76
  77   val wdog = Module(new WatchdogTimer)
  78   io.wdog_rst := wdog.io.rst
  79   wdog.io.corerst := pmu.io.control.corerst
  80   interrupts(0) := wdog.io.ip(0)
  81
  82   // If there are multiple lfclks to choose from, we can mux them here.
  83   io.lfclk := io.lfextclk
  84
  85   val backupRegs = Seq.fill(c.nBackupRegs)(Reg(UInt(width = c.regBytes * 8)))
  86   val backupRegMap =
  87     for ((reg, i) <- backupRegs.zipWithIndex)
  88       yield (c.backupRegOffset + c.regBytes*i) -> Seq(RegField(reg.getWidth, RegReadFn(reg), RegWriteFn(reg)))
  89
  90   regmap((backupRegMap ++
  91     GenericTimer.timerRegMap(wdog, c.wdogOffset, c.regBytes) ++
  92     GenericTimer.timerRegMap(rtc, c.rtcOffset, c.regBytes) ++
  93     pmuRegMap):_*)
  94
  95 }
  96
  97 class TLMockAON(w: Int, c: MockAONParams)(implicit p: Parameters)
  98   extends TLRegisterRouter(c.address, "aon", Seq("sifive,aon0"), interrupts = 2, size = c.size, beatBytes = w, concurrency = 1)(
  99   new TLRegBundle(c, _)    with HasMockAONBundleContents)(
 100   new TLRegModule(c, _, _) with HasMockAONModuleContents)