src/main/scala/devices/pwm/PWMPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.pwm
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Field
   6 import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
   7 import freechips.rocketchip.chip.HasSystemNetworks
   8 import freechips.rocketchip.tilelink.TLFragmenter
   9 import freechips.rocketchip.util.HeterogeneousBag
  10 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
  11
  12 class PWMPortIO(val c: PWMParams) extends Bundle {
  13   val port = Vec(c.ncmp, Bool()).asOutput
  14   override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
  15 }
  16
  17 class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle {
  18
  19   val pwm: Vec[T] = Vec(c.ncmp, pingen())
  20
  21   def fromPWMPort(port: PWMPortIO) {
  22     (pwm zip port.port)  foreach {case (pin, port) =>
  23       pin.outputPin(port)
  24     }
  25   }
  26 }
  27
  28 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
  29
  30 trait HasPeripheryPWM extends HasSystemNetworks {
  31   val pwmParams = p(PeripheryPWMKey)
  32   val pwms = pwmParams map { params =>
  33     val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
  34     pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
  35     intBus.intnode := pwm.intnode
  36     pwm
  37   }
  38 }
  39
  40 trait HasPeripheryPWMBundle {
  41   val pwm: HeterogeneousBag[PWMPortIO]
  42
  43 }
  44
  45 trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
  46   val outer: HasPeripheryPWM
  47   val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
  48
  49   (pwm zip outer.pwms) foreach { case (io, device) =>
  50     io.port := device.module.io.gpio
  51   }
  52 }