src/main/scala/devices/pwm/PWMPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.pwm
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Field
   6 import freechips.rocketchip.subsystem.BaseSubsystem
   7 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
   8 import freechips.rocketchip.util.HeterogeneousBag
   9 import sifive.blocks.devices.pinctrl.{Pin}
  10
  11 class PWMPortIO(val c: PWMParams) extends Bundle {
  12   val port = Vec(c.ncmp, Bool()).asOutput
  13 }
  14
  15
  16 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
  17
  18 trait HasPeripheryPWM { this: BaseSubsystem =>
  19   val pwmParams = p(PeripheryPWMKey)
  20   val pwms = pwmParams.zipWithIndex.map { case(params, i) =>
  21     val name = Some(s"pwm_$i")
  22     val pwm = LazyModule(new TLPWM(pbus.beatBytes, params)).suggestName(name)
  23     pbus.toVariableWidthSlave(name) { pwm.node }
  24     ibus.fromSync := pwm.intnode
  25     pwm
  26   }
  27 }
  28
  29 trait HasPeripheryPWMBundle {
  30   val pwm: HeterogeneousBag[PWMPortIO]
  31
  32 }
  33
  34 trait HasPeripheryPWMModuleImp extends LazyModuleImp with HasPeripheryPWMBundle {
  35   val outer: HasPeripheryPWM
  36   val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
  37
  38   (pwm zip outer.pwms) foreach { case (io, device) =>
  39     io.port := device.module.io.gpio
  40   }
  41 }