1 // See LICENSE for license details.
2 package sifive.blocks.devices.pwm
6 import diplomacy.LazyModule
9 HasTopLevelNetworksBundle,
10 HasTopLevelNetworksModule
12 import uncore.tilelink2.TLFragmenter
13 import util.HeterogeneousBag
15 import sifive.blocks.devices.gpio._
17 class PWMPortIO(c: PWMParams) extends Bundle {
18 val port = Vec(c.ncmp, Bool()).asOutput
19 override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
22 class PWMPinsIO(c: PWMParams) extends Bundle {
23 val pwm = Vec(c.ncmp, new GPIOPin)
26 class PWMGPIOPort(c: PWMParams) extends Module {
28 val pwm = new PWMPortIO(c).flip()
29 val pins = new PWMPinsIO(c)
32 GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
35 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
37 trait HasPeripheryPWM extends HasTopLevelNetworks {
38 val pwmParams = p(PeripheryPWMKey)
39 val pwms = pwmParams map { params =>
40 val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
41 pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
42 intBus.intnode := pwm.intnode
47 trait HasPeripheryPWMBundle extends HasTopLevelNetworksBundle {
48 val outer: HasPeripheryPWM
49 val pwms = HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_)))
52 trait HasPeripheryPWMModule extends HasTopLevelNetworksModule {
53 val outer: HasPeripheryPWM
54 val io: HasPeripheryPWMBundle
56 (io.pwms zip outer.pwms) foreach { case (io, device) =>
57 io.port := device.module.io.gpio