1 // See LICENSE for license details.
2 package sifive.blocks.devices.spi
6 abstract class SPIBundle(private val c: SPIParamsBase) extends Bundle
8 class SPIDataIO extends Bundle {
14 class SPIPortIO(c: SPIParamsBase) extends SPIBundle(c) {
15 val sck = Bool(OUTPUT)
16 val dq = Vec(4, new SPIDataIO)
17 val cs = Vec(c.csWidth, Bool(OUTPUT))
20 trait HasSPIProtocol {
21 val proto = Bits(width = SPIProtocol.width)
24 val endian = Bits(width = SPIEndian.width)
26 class SPIFormat(c: SPIParamsBase) extends SPIBundle(c)
29 val iodir = Bits(width = SPIDirection.width)
32 trait HasSPILength extends SPIBundle {
33 val len = UInt(width = c.lengthBits)
36 class SPIClocking(c: SPIParamsBase) extends SPIBundle(c) {
37 val div = UInt(width = c.divisorBits)
42 class SPIChipSelect(c: SPIParamsBase) extends SPIBundle(c) {
43 val id = UInt(width = c.csIdBits)
44 val dflt = Vec(c.csWidth, Bool())
46 def toggle(en: Bool): Vec[Bool] = {
48 val out = Cat(dflt.reverse) ^ mask
49 Vec.tabulate(c.csWidth)(out(_))
54 val mode = Bits(width = SPICSMode.width)
57 class SPIDelay(c: SPIParamsBase) extends SPIBundle(c) {
58 val cssck = UInt(width = c.delayBits)
59 val sckcs = UInt(width = c.delayBits)
60 val intercs = UInt(width = c.delayBits)
61 val interxfr = UInt(width = c.delayBits)
64 class SPIWatermark(c: SPIParamsBase) extends SPIBundle(c) {
65 val tx = UInt(width = c.txDepthBits)
66 val rx = UInt(width = c.rxDepthBits)
69 class SPIControl(c: SPIParamsBase) extends SPIBundle(c) {
70 val fmt = new SPIFormat(c) with HasSPILength
71 val sck = new SPIClocking(c)
72 val cs = new SPIChipSelect(c) with HasSPICSMode
73 val dla = new SPIDelay(c)
74 val wm = new SPIWatermark(c)
78 def init(c: SPIParamsBase): SPIControl = {
79 val ctrl = Wire(new SPIControl(c))
80 ctrl.fmt.proto := SPIProtocol.Single
81 ctrl.fmt.iodir := SPIDirection.Rx
82 ctrl.fmt.endian := SPIEndian.MSB
83 ctrl.fmt.len := UInt(math.min(c.frameBits, 8))
84 ctrl.sck.div := UInt(3)
85 ctrl.sck.pol := Bool(false)
86 ctrl.sck.pha := Bool(false)
88 ctrl.cs.dflt.foreach { _ := Bool(true) }
89 ctrl.cs.mode := SPICSMode.Auto
90 ctrl.dla.cssck := UInt(1)
91 ctrl.dla.sckcs := UInt(1)
92 ctrl.dla.intercs := UInt(1)
93 ctrl.dla.interxfr := UInt(0)
100 class SPIInterrupts extends Bundle {