src/main/scala/devices/spi/SPIPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.spi
   3
   4 import Chisel._
   5 import diplomacy.LazyModule
   6 import uncore.tilelink2._
   7 import rocketchip.{TopNetwork,TopNetworkModule}
   8 import util.HeterogeneousBag
   9
  10 trait PeripherySPI {
  11   this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
  12   val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
  13     val spi = LazyModule(new TLSPI(c))
  14     spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
  15     intBus.intnode := spi.intnode
  16     spi
  17   }
  18 }
  19
  20 trait PeripherySPIBundle {
  21   this: { val spiConfigs: Seq[SPIConfig] } =>
  22   val spis = HeterogeneousBag(spiConfigs.map(new SPIPortIO(_)))
  23 }
  24
  25 trait PeripherySPIModule {
  26   this: TopNetworkModule {
  27     val spiConfigs: Seq[SPIConfig]
  28     val outer: PeripherySPI
  29     val io: PeripherySPIBundle
  30   } =>
  31   (io.spis zip outer.spi).foreach { case (io, device) =>
  32     io <> device.module.io.port
  33   }
  34 }
  35
  36
  37 trait PeripherySPIFlash {
  38   this: TopNetwork { val spiFlashConfig: SPIFlashConfig } =>
  39   val qspi = LazyModule(new TLSPIFlash(spiFlashConfig))
  40   qspi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
  41   qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusConfig.beatBytes)(peripheryBus.node))
  42   intBus.intnode := qspi.intnode
  43 }
  44
  45 trait PeripherySPIFlashBundle {
  46   this: { val spiFlashConfig: SPIFlashConfig } =>
  47   val qspi = new SPIPortIO(spiFlashConfig)
  48 }
  49
  50 trait PeripherySPIFlashModule {
  51   this: TopNetworkModule {
  52     val spiConfigs: Seq[SPIConfig]
  53     val outer: PeripherySPIFlash
  54     val io: PeripherySPIFlashBundle
  55   } =>
  56   io.qspi <> outer.qspi.module.io.port
  57 }