1 // See LICENSE for license details.
2 package sifive.blocks.devices.spi
5 import diplomacy.LazyModule
6 import uncore.tilelink2._
7 import rocketchip.{TopNetwork,TopNetworkModule}
10 this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
11 val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
12 val spi = LazyModule(new TLSPI(c))
13 spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
14 intBus.intnode := spi.intnode
19 trait PeripherySPIBundle {
20 this: { val spiConfigs: Seq[SPIConfig] } =>
21 val spi_bc = spiConfigs.map(_.bc).reduce(_.union(_))
22 val spis = Vec(spiConfigs.size, new SPIPortIO(spi_bc.toSPIConfig))
25 trait PeripherySPIModule {
26 this: TopNetworkModule {
27 val spiConfigs: Seq[SPIConfig]
28 val outer: PeripherySPI
29 val io: PeripherySPIBundle
31 (io.spis zip outer.spi).foreach { case (io, device) =>
32 io <> device.module.io.port
37 trait PeripherySPIFlash {
38 this: TopNetwork { val spiFlashConfig: SPIFlashConfig } =>
39 val qspi = LazyModule(new TLSPIFlash(spiFlashConfig))
40 qspi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
41 qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusConfig.beatBytes)(peripheryBus.node))
42 intBus.intnode := qspi.intnode
45 trait PeripherySPIFlashBundle {
46 this: { val spiFlashConfig: SPIFlashConfig } =>
47 val qspi = new SPIPortIO(spiFlashConfig)
50 trait PeripherySPIFlashModule {
51 this: TopNetworkModule {
52 val spiConfigs: Seq[SPIConfig]
53 val outer: PeripherySPIFlash
54 val io: PeripherySPIFlashBundle
56 io.qspi <> outer.qspi.module.io.port