1 // See LICENSE for license details.
2 package sifive.blocks.devices.spi
5 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
7 class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
10 val dq: Vec[T] = Vec(4, pingen())
11 val cs: Vec[T] = Vec(c.csWidth, pingen())
13 def fromSPIPort(spi: SPIPortIO, syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
15 sck.outputPin(spi.sck, ds = driveStrength)
17 (dq zip spi.dq).foreach {case (p, s) =>
18 p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
21 s.i := ShiftRegister(p.i.ival, syncStages)
24 (cs zip spi.cs) foreach { case (c, s) =>
25 c.outputPin(s, ds = driveStrength)