src/main/scala/devices/spi/SPIPins.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.spi
   3
   4 import Chisel._
   5 import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
   6
   7 class SPIPinsIO(c: SPIParamsBase) extends SPIBundle(c) {
   8   val sck = new GPIOPin
   9   val dq = Vec(4, new GPIOPin)
  10   val cs = Vec(c.csWidth, new GPIOPin)
  11 }
  12
  13 class SPIGPIOPort(c: SPIParamsBase, syncStages: Int = 0, driveStrength: Bool = Bool(false)) extends Module {
  14   val io = new SPIBundle(c) {
  15     val spi = new SPIPortIO(c).flip
  16     val pins = new SPIPinsIO(c)
  17   }
  18
  19   GPIOOutputPinCtrl(io.pins.sck, io.spi.sck, ds = driveStrength)
  20
  21   GPIOOutputPinCtrl(io.pins.dq, Bits(0, io.spi.dq.size))
  22   (io.pins.dq zip io.spi.dq).foreach {
  23     case (p, s) =>
  24       p.o.oval := s.o
  25       p.o.oe  := s.oe
  26       p.o.ie  := ~s.oe
  27       p.o.pue := Bool(true)
  28       p.o.ds  := driveStrength
  29       s.i := ShiftRegister(p.i.ival, syncStages)
  30   }
  31
  32   GPIOOutputPinCtrl(io.pins.cs, io.spi.cs.asUInt)
  33   io.pins.cs.foreach(_.o.ds := driveStrength)
  34 }