src/main/scala/devices/spi/TLSPIFlash.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.spi
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Parameters
   6 import freechips.rocketchip.diplomacy._
   7 import freechips.rocketchip.regmapper._
   8 import freechips.rocketchip.tilelink._
   9 import freechips.rocketchip.util.HeterogeneousBag
  10
  11 trait SPIFlashParamsBase extends SPIParamsBase {
  12   val fAddress: BigInt
  13   val fSize: BigInt
  14
  15   val insnAddrBytes: Int
  16   val insnPadLenBits: Int
  17   lazy val insnCmdBits = frameBits
  18   lazy val insnAddrBits = insnAddrBytes * frameBits
  19   lazy val insnAddrLenBits = log2Floor(insnAddrBytes) + 1
  20 }
  21
  22 case class SPIFlashParams(
  23     rAddress: BigInt,
  24     fAddress: BigInt,
  25     rSize: BigInt = 0x1000,
  26     fSize: BigInt = 0x20000000,
  27     rxDepth: Int = 8,
  28     txDepth: Int = 8,
  29     csWidth: Int = 1,
  30     delayBits: Int = 8,
  31     divisorBits: Int = 12,
  32     sampleDelay: Int = 2)
  33   extends SPIFlashParamsBase {
  34   val frameBits = 8
  35   val insnAddrBytes = 4
  36   val insnPadLenBits = 4
  37
  38   require(insnPadLenBits <= delayBits)
  39   require(sampleDelay >= 0)
  40 }
  41
  42 class SPIFlashTopBundle(i: HeterogeneousBag[Vec[Bool]], r: HeterogeneousBag[TLBundle], val f: HeterogeneousBag[TLBundle]) extends SPITopBundle(i, r)
  43
  44 class SPIFlashTopModule[B <: SPIFlashTopBundle]
  45     (c: SPIFlashParamsBase, bundle: => B, outer: TLSPIFlashBase)
  46   extends SPITopModule(c, bundle, outer) {
  47
  48   val flash = Module(new SPIFlashMap(c))
  49   val arb = Module(new SPIArbiter(c, 2))
  50
  51   private val f = io.tl.f.head
  52   // Tie unused channels
  53   f.b.valid := Bool(false)
  54   f.c.ready := Bool(true)
  55   f.e.ready := Bool(true)
  56
  57   val a = Reg(f.a.bits)
  58   val a_msb = log2Ceil(c.fSize) - 1
  59
  60   when (f.a.fire()) {
  61     a := f.a.bits
  62   }
  63
  64   flash.io.addr.bits.next := f.a.bits.address(a_msb, 0)
  65   flash.io.addr.bits.hold := a.address(a_msb, 0)
  66   flash.io.addr.valid := f.a.valid
  67   f.a.ready := flash.io.addr.ready
  68
  69   f.d.bits := outer.fnode.edgesIn.head.AccessAck(a, UInt(0), flash.io.data.bits)
  70   f.d.valid := flash.io.data.valid
  71   flash.io.data.ready := f.d.ready
  72
  73   val insn = Reg(init = SPIFlashInsn.init(c))
  74   val flash_en = Reg(init = Bool(true))
  75
  76   flash.io.ctrl.insn := insn
  77   flash.io.ctrl.fmt <> ctrl.fmt
  78   flash.io.en := flash_en
  79   arb.io.sel := !flash_en
  80
  81   protected val regmapFlash = Seq(
  82     SPICRs.insnmode -> Seq(RegField(1, flash_en)),
  83     SPICRs.insnfmt -> Seq(
  84       RegField(1, insn.cmd.en),
  85       RegField(c.insnAddrLenBits, insn.addr.len),
  86       RegField(c.insnPadLenBits, insn.pad.cnt)),
  87     SPICRs.insnproto -> Seq(
  88       RegField(SPIProtocol.width, insn.cmd.proto),
  89       RegField(SPIProtocol.width, insn.addr.proto),
  90       RegField(SPIProtocol.width, insn.data.proto)),
  91     SPICRs.insncmd -> Seq(RegField(c.insnCmdBits, insn.cmd.code)),
  92     SPICRs.insnpad -> Seq(RegField(c.frameBits, insn.pad.code)))
  93 }
  94
  95 abstract class TLSPIFlashBase(w: Int, c: SPIFlashParamsBase)(implicit p: Parameters) extends TLSPIBase(w,c)(p) {
  96   require(isPow2(c.fSize))
  97   val fnode = TLManagerNode(1, TLManagerParameters(
  98     address     = Seq(AddressSet(c.fAddress, c.fSize-1)),
  99     resources   = device.reg("mem"),
 100     regionType  = RegionType.UNCACHED,
 101     executable  = true,
 102     supportsGet = TransferSizes(1, 1),
 103     fifoId      = Some(0)))
 104 }
 105
 106 class TLSPIFlash(w: Int, c: SPIFlashParams)(implicit p: Parameters) extends TLSPIFlashBase(w,c)(p) {
 107   lazy val module = new SPIFlashTopModule(c,
 108     new SPIFlashTopBundle(intnode.bundleOut, rnode.bundleIn, fnode.bundleIn), this) {
 109
 110     arb.io.inner(0) <> flash.io.link
 111     arb.io.inner(1) <> fifo.io.link
 112     mac.io.link <> arb.io.outer
 113
 114     rnode.regmap(regmapBase ++ regmapFlash:_*)
 115   }
 116 }