1 // See LICENSE for license details.
2 package sifive.blocks.devices.uart
5 import freechips.rocketchip.config.Field
6 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
7 import freechips.rocketchip.chip.HasSystemNetworks
8 import freechips.rocketchip.tilelink.TLFragmenter
9 import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
10 import sifive.blocks.util.ShiftRegisterInit
12 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
14 trait HasPeripheryUART extends HasSystemNetworks {
15 val uartParams = p(PeripheryUARTKey)
16 val uarts = uartParams map { params =>
17 val uart = LazyModule(new TLUART(peripheryBusBytes, params))
18 uart.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
19 intBus.intnode := uart.intnode
24 trait HasPeripheryUARTBundle {
25 val uarts: Vec[UARTPortIO]
27 def tieoffUARTs(dummy: Int = 1) {
28 uarts.foreach { _.rxd := UInt(1) }
33 trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
34 val outer: HasPeripheryUART
35 val uarts = IO(Vec(outer.uartParams.size, new UARTPortIO))
37 (uarts zip outer.uarts).foreach { case (io, device) =>
38 io <> device.module.io.port
42 class UARTPins(pingen: () => Pin) extends Bundle {
46 def fromUARTPort(uart: UARTPortIO, syncStages: Int = 0) {
47 txd.outputPin(uart.txd)
48 val rxd_t = rxd.inputPin()
49 uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))