src/main/scala/devices/uart/UARTPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.uart
   3
   4 import Chisel._
   5 import chisel3.experimental.{withClockAndReset}
   6 import freechips.rocketchip.config.Field
   7 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
   8 import freechips.rocketchip.subsystem.{BaseSubsystem, PeripheryBusKey}
   9
  10 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
  11
  12 trait HasPeripheryUART { this: BaseSubsystem =>
  13   private val divinit = (p(PeripheryBusKey).frequency / 115200).toInt
  14   val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
  15   val uarts = uartParams.zipWithIndex.map { case(params, i) =>
  16     val name = Some(s"uart_$i")
  17     val uart = LazyModule(new TLUART(pbus.beatBytes, params)).suggestName(name)
  18     pbus.toVariableWidthSlave(name) { uart.node }
  19     ibus.fromSync := uart.intnode
  20     uart
  21   }
  22 }
  23
  24 trait HasPeripheryUARTBundle {
  25   val uart: Vec[UARTPortIO]
  26
  27   def tieoffUARTs(dummy: Int = 1) {
  28     uart.foreach { _.rxd := UInt(1) }
  29   }
  30
  31 }
  32
  33 trait HasPeripheryUARTModuleImp extends LazyModuleImp with HasPeripheryUARTBundle {
  34   val outer: HasPeripheryUART
  35   val uart = IO(Vec(outer.uartParams.size, new UARTPortIO))
  36
  37   (uart zip outer.uarts).foreach { case (io, device) =>
  38     io <> device.module.io.port
  39   }
  40 }