src/main/scala/devices/uart/UARTPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.uart
   3
   4 import Chisel._
   5 import chisel3.experimental.{withClockAndReset}
   6 import freechips.rocketchip.config.Field
   7 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
   8 import freechips.rocketchip.chip.HasSystemNetworks
   9 import freechips.rocketchip.tilelink.TLFragmenter
  10 import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
  11 import sifive.blocks.util.ShiftRegisterInit
  12
  13 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
  14
  15 trait HasPeripheryUART extends HasSystemNetworks {
  16   val uartParams = p(PeripheryUARTKey)
  17   val uarts = uartParams map { params =>
  18     val uart = LazyModule(new TLUART(peripheryBusBytes, params))
  19     uart.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
  20     intBus.intnode := uart.intnode
  21     uart
  22   }
  23 }
  24
  25 trait HasPeripheryUARTBundle {
  26   val uart: Vec[UARTPortIO]
  27
  28   def tieoffUARTs(dummy: Int = 1) {
  29     uart.foreach { _.rxd := UInt(1) }
  30   }
  31
  32 }
  33
  34 trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
  35   val outer: HasPeripheryUART
  36   val uart = IO(Vec(outer.uartParams.size, new UARTPortIO))
  37
  38   (uart zip outer.uarts).foreach { case (io, device) =>
  39     io <> device.module.io.port
  40   }
  41 }
  42
  43 class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
  44   val rxd = pingen()
  45   val txd = pingen()
  46
  47   def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
  48     withClockAndReset(clock, reset) {
  49       txd.outputPin(uart.txd)
  50       val rxd_t = rxd.inputPin()
  51       uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
  52     }
  53   }
  54 }
  55