1 // See LICENSE for license details.
2 package sifive.blocks.devices.uart
5 import chisel3.experimental.{withClockAndReset}
6 import freechips.rocketchip.config.Field
7 import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
8 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
10 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
12 trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
13 private val divinit = (p(PeripheryBusKey).frequency / 115200).toInt
14 val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
15 val uarts = uartParams map { params =>
16 val uart = LazyModule(new TLUART(pbus.beatBytes, params))
17 uart.node := pbus.toVariableWidthSlaves
18 ibus.fromSync := uart.intnode
23 trait HasPeripheryUARTBundle {
24 val uart: Vec[UARTPortIO]
26 def tieoffUARTs(dummy: Int = 1) {
27 uart.foreach { _.rxd := UInt(1) }
32 trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
33 val outer: HasPeripheryUART
34 val uart = IO(Vec(outer.uartParams.size, new UARTPortIO))
36 (uart zip outer.uarts).foreach { case (io, device) =>
37 io <> device.module.io.port