src/main/scala/devices/uart/UARTPins.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.uart
   3
   4 import Chisel._
   5 import chisel3.experimental.{withClockAndReset}
   6 import freechips.rocketchip.config.Field
   7 import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
   8 import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
   9 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
  10 import sifive.blocks.devices.pinctrl.{Pin}
  11
  12
  13 class UARTSignals[T <: Data] (pingen: () => T) extends Bundle {
  14   val rxd = pingen()
  15   val txd = pingen()
  16
  17   override def cloneType: this.type =
  18     this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
  19 }
  20
  21 class UARTPins[T <: Pin] (pingen: () => T) extends UARTSignals[T](pingen, c) {
  22   override def cloneType: this.type =
  23     this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
  24
  25   def fromPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
  26     withClockAndReset(clock, reset) {
  27       txd.outputPin(uart.txd)
  28       val rxd_t = rxd.inputPin()
  29       uart.rxd := SyncResetSynchronizerShiftReg(rxd_t, syncStages, init = Bool(true), name = Some("uart_rxd_sync"))
  30     }
  31   }
  32 }
  33