src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.xilinxvc707mig
   3
   4 import Chisel._
   5 import chisel3.experimental.{Analog,attach}
   6 import freechips.rocketchip.amba.axi4._
   7 import freechips.rocketchip.config.Parameters
   8 import freechips.rocketchip.coreplex._
   9 import freechips.rocketchip.diplomacy._
  10 import freechips.rocketchip.tilelink._
  11 import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
  12
  13 case class XilinxVC707MIGParams(
  14   address : Seq[AddressSet]
  15 )
  16
  17 class XilinxVC707MIGPads(depth : BigInt) extends VC707MIGIODDR(depth) {
  18   def this(c : XilinxVC707MIGParams) {
  19     this(AddressRange.fromSets(c.address).head.size)
  20   }
  21 }
  22
  23 class XilinxVC707MIGIO(depth : BigInt) extends VC707MIGIODDR(depth) with VC707MIGIOClocksReset
  24
  25 class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule {
  26   val ranges = AddressRange.fromSets(c.address)
  27   require (ranges.size == 1, "DDR range must be contiguous")
  28   val offset = ranges.head.base
  29   val depth = ranges.head.size
  30   require((depth==0x40000000L) || (depth==0x100000000L)) //1GB or 4GB depth
  31
  32   val device = new MemoryDevice
  33   val node = TLInputNode()
  34   val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
  35       slaves = Seq(AXI4SlaveParameters(
  36       address       = c.address,
  37       resources     = device.reg,
  38       regionType    = RegionType.UNCACHED,
  39       executable    = true,
  40       supportsWrite = TransferSizes(1, 256*8),
  41       supportsRead  = TransferSizes(1, 256*8))),
  42     beatBytes = 8)))
  43
  44   val xing    = LazyModule(new TLAsyncCrossing)
  45   val toaxi4  = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1))
  46   val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
  47   val deint   = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
  48   val yank    = LazyModule(new AXI4UserYanker)
  49   val buffer  = LazyModule(new AXI4Buffer)
  50
  51   xing.node := node
  52   val monitor = (toaxi4.node := xing.node)
  53   axi4 := buffer.node
  54   buffer.node := yank.node
  55   yank.node := deint.node
  56   deint.node := indexer.node
  57   indexer.node := toaxi4.node
  58
  59   lazy val module = new LazyModuleImp(this) {
  60     val io = new Bundle {
  61       val port = new XilinxVC707MIGIO(depth)
  62       val tl = node.bundleIn
  63     }
  64
  65     //MIG black box instantiation
  66     val blackbox = Module(new vc707mig(depth))
  67
  68     //pins to top level
  69
  70     //inouts
  71     attach(io.port.ddr3_dq,blackbox.io.ddr3_dq)
  72     attach(io.port.ddr3_dqs_n,blackbox.io.ddr3_dqs_n)
  73     attach(io.port.ddr3_dqs_p,blackbox.io.ddr3_dqs_p)
  74
  75     //outputs
  76     io.port.ddr3_addr         := blackbox.io.ddr3_addr
  77     io.port.ddr3_ba           := blackbox.io.ddr3_ba
  78     io.port.ddr3_ras_n        := blackbox.io.ddr3_ras_n
  79     io.port.ddr3_cas_n        := blackbox.io.ddr3_cas_n
  80     io.port.ddr3_we_n         := blackbox.io.ddr3_we_n
  81     io.port.ddr3_reset_n      := blackbox.io.ddr3_reset_n
  82     io.port.ddr3_ck_p         := blackbox.io.ddr3_ck_p
  83     io.port.ddr3_ck_n         := blackbox.io.ddr3_ck_n
  84     io.port.ddr3_cke          := blackbox.io.ddr3_cke
  85     io.port.ddr3_cs_n         := blackbox.io.ddr3_cs_n
  86     io.port.ddr3_dm           := blackbox.io.ddr3_dm
  87     io.port.ddr3_odt          := blackbox.io.ddr3_odt
  88
  89     //inputs
  90     //NO_BUFFER clock
  91     blackbox.io.sys_clk_i     := io.port.sys_clk_i
  92
  93     //user interface signals
  94     val axi_async = axi4.bundleIn(0)
  95     xing.module.io.in_clock := clock
  96     xing.module.io.in_reset := reset
  97     xing.module.io.out_clock := blackbox.io.ui_clk
  98     xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
  99     (Seq(toaxi4, indexer, deint, yank, buffer) ++ monitor) foreach { lm =>
 100       lm.module.clock := blackbox.io.ui_clk
 101       lm.module.reset := blackbox.io.ui_clk_sync_rst
 102     }
 103
 104     io.port.ui_clk            := blackbox.io.ui_clk
 105     io.port.ui_clk_sync_rst   := blackbox.io.ui_clk_sync_rst
 106     io.port.mmcm_locked       := blackbox.io.mmcm_locked
 107     blackbox.io.aresetn       := io.port.aresetn
 108     blackbox.io.app_sr_req    := Bool(false)
 109     blackbox.io.app_ref_req   := Bool(false)
 110     blackbox.io.app_zq_req    := Bool(false)
 111     //app_sr_active           := unconnected
 112     //app_ref_ack             := unconnected
 113     //app_zq_ack              := unconnected
 114
 115     val awaddr = axi_async.aw.bits.addr - UInt(offset)
 116     val araddr = axi_async.ar.bits.addr - UInt(offset)
 117
 118     //slave AXI interface write address ports
 119     blackbox.io.s_axi_awid    := axi_async.aw.bits.id
 120     blackbox.io.s_axi_awaddr  := awaddr //truncated
 121     blackbox.io.s_axi_awlen   := axi_async.aw.bits.len
 122     blackbox.io.s_axi_awsize  := axi_async.aw.bits.size
 123     blackbox.io.s_axi_awburst := axi_async.aw.bits.burst
 124     blackbox.io.s_axi_awlock  := axi_async.aw.bits.lock
 125     blackbox.io.s_axi_awcache := UInt("b0011")
 126     blackbox.io.s_axi_awprot  := axi_async.aw.bits.prot
 127     blackbox.io.s_axi_awqos   := axi_async.aw.bits.qos
 128     blackbox.io.s_axi_awvalid := axi_async.aw.valid
 129     axi_async.aw.ready        := blackbox.io.s_axi_awready
 130
 131     //slave interface write data ports
 132     blackbox.io.s_axi_wdata   := axi_async.w.bits.data
 133     blackbox.io.s_axi_wstrb   := axi_async.w.bits.strb
 134     blackbox.io.s_axi_wlast   := axi_async.w.bits.last
 135     blackbox.io.s_axi_wvalid  := axi_async.w.valid
 136     axi_async.w.ready         := blackbox.io.s_axi_wready
 137
 138     //slave interface write response
 139     blackbox.io.s_axi_bready  := axi_async.b.ready
 140     axi_async.b.bits.id       := blackbox.io.s_axi_bid
 141     axi_async.b.bits.resp     := blackbox.io.s_axi_bresp
 142     axi_async.b.valid         := blackbox.io.s_axi_bvalid
 143
 144     //slave AXI interface read address ports
 145     blackbox.io.s_axi_arid    := axi_async.ar.bits.id
 146     blackbox.io.s_axi_araddr  := araddr // truncated
 147     blackbox.io.s_axi_arlen   := axi_async.ar.bits.len
 148     blackbox.io.s_axi_arsize  := axi_async.ar.bits.size
 149     blackbox.io.s_axi_arburst := axi_async.ar.bits.burst
 150     blackbox.io.s_axi_arlock  := axi_async.ar.bits.lock
 151     blackbox.io.s_axi_arcache := UInt("b0011")
 152     blackbox.io.s_axi_arprot  := axi_async.ar.bits.prot
 153     blackbox.io.s_axi_arqos   := axi_async.ar.bits.qos
 154     blackbox.io.s_axi_arvalid := axi_async.ar.valid
 155     axi_async.ar.ready        := blackbox.io.s_axi_arready
 156
 157     //slace AXI interface read data ports
 158     blackbox.io.s_axi_rready  := axi_async.r.ready
 159     axi_async.r.bits.id       := blackbox.io.s_axi_rid
 160     axi_async.r.bits.data     := blackbox.io.s_axi_rdata
 161     axi_async.r.bits.resp     := blackbox.io.s_axi_rresp
 162     axi_async.r.bits.last     := blackbox.io.s_axi_rlast
 163     axi_async.r.valid         := blackbox.io.s_axi_rvalid
 164
 165     //misc
 166     io.port.init_calib_complete := blackbox.io.init_calib_complete
 167     blackbox.io.sys_rst       :=io.port.sys_rst
 168     //mig.device_temp         :- unconnceted
 169   }
 170 }