src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.xilinxvc707mig
   3
   4 import Chisel._
   5 import chisel3.experimental.{Analog,attach}
   6 import freechips.rocketchip.amba.axi4._
   7 import freechips.rocketchip.config.Parameters
   8 import freechips.rocketchip.coreplex._
   9 import freechips.rocketchip.diplomacy._
  10 import freechips.rocketchip.tilelink._
  11 import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
  12
  13 case class XilinxVC707MIGParams(
  14   depthGB : Int
  15 )
  16
  17 class XilinxVC707MIGPads(depthGB : Integer) extends VC707MIGIODDR(depthGB)
  18
  19 class XilinxVC707MIGIO(depthGB : Integer) extends VC707MIGIODDR(depthGB) with VC707MIGIOClocksReset
  20
  21 class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule {
  22   require((c.depthGB == 1) || (c.depthGB == 4))
  23
  24   // Suppoted address map configuratons
  25   val address = if(c.depthGB == 1) Seq(AddressSet(0x80000000L ,  0x80000000L-1))       //2GB   @ 2GB
  26                 else Seq(AddressSet(0x80000000L,   0x80000000L-1),       //2GB   @ 2GB
  27                          AddressSet(0x2080000000L, 0x80000000L-1))       //2GB   @ 130GB
  28
  29   val device = new MemoryDevice
  30   val node = TLInputNode()
  31   val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
  32       slaves = Seq(AXI4SlaveParameters(
  33       address       = address,
  34       resources     = device.reg,
  35       regionType    = RegionType.UNCACHED,
  36       executable    = true,
  37       supportsWrite = TransferSizes(1, 256*8),
  38       supportsRead  = TransferSizes(1, 256*8))),
  39     beatBytes = 8)))
  40
  41   val xing    = LazyModule(new TLAsyncCrossing)
  42   val toaxi4  = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1))
  43   val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
  44   val deint   = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
  45   val yank    = LazyModule(new AXI4UserYanker)
  46   val buffer  = LazyModule(new AXI4Buffer)
  47
  48   xing.node := node
  49   val monitor = (toaxi4.node := xing.node)
  50   axi4 := buffer.node
  51   buffer.node := yank.node
  52   yank.node := deint.node
  53   deint.node := indexer.node
  54   indexer.node := toaxi4.node
  55
  56   lazy val module = new LazyModuleImp(this) {
  57     val io = new Bundle {
  58       val port = new XilinxVC707MIGIO(c.depthGB)
  59       val tl = node.bundleIn
  60     }
  61
  62     //MIG black box instantiation
  63     val blackbox = Module(new vc707mig(c.depthGB))
  64
  65     //pins to top level
  66
  67     //inouts
  68     attach(io.port.ddr3_dq,blackbox.io.ddr3_dq)
  69     attach(io.port.ddr3_dqs_n,blackbox.io.ddr3_dqs_n)
  70     attach(io.port.ddr3_dqs_p,blackbox.io.ddr3_dqs_p)
  71
  72     //outputs
  73     io.port.ddr3_addr         := blackbox.io.ddr3_addr
  74     io.port.ddr3_ba           := blackbox.io.ddr3_ba
  75     io.port.ddr3_ras_n        := blackbox.io.ddr3_ras_n
  76     io.port.ddr3_cas_n        := blackbox.io.ddr3_cas_n
  77     io.port.ddr3_we_n         := blackbox.io.ddr3_we_n
  78     io.port.ddr3_reset_n      := blackbox.io.ddr3_reset_n
  79     io.port.ddr3_ck_p         := blackbox.io.ddr3_ck_p
  80     io.port.ddr3_ck_n         := blackbox.io.ddr3_ck_n
  81     io.port.ddr3_cke          := blackbox.io.ddr3_cke
  82     io.port.ddr3_cs_n         := blackbox.io.ddr3_cs_n
  83     io.port.ddr3_dm           := blackbox.io.ddr3_dm
  84     io.port.ddr3_odt          := blackbox.io.ddr3_odt
  85
  86     //inputs
  87     //NO_BUFFER clock
  88     blackbox.io.sys_clk_i     := io.port.sys_clk_i
  89
  90     //user interface signals
  91     val axi_async = axi4.bundleIn(0)
  92     xing.module.io.in_clock := clock
  93     xing.module.io.in_reset := reset
  94     xing.module.io.out_clock := blackbox.io.ui_clk
  95     xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
  96     (Seq(toaxi4, indexer, deint, yank, buffer) ++ monitor) foreach { lm =>
  97       lm.module.clock := blackbox.io.ui_clk
  98       lm.module.reset := blackbox.io.ui_clk_sync_rst
  99     }
 100
 101     io.port.ui_clk            := blackbox.io.ui_clk
 102     io.port.ui_clk_sync_rst   := blackbox.io.ui_clk_sync_rst
 103     io.port.mmcm_locked       := blackbox.io.mmcm_locked
 104     blackbox.io.aresetn       := io.port.aresetn
 105     blackbox.io.app_sr_req    := Bool(false)
 106     blackbox.io.app_ref_req   := Bool(false)
 107     blackbox.io.app_zq_req    := Bool(false)
 108     //app_sr_active           := unconnected
 109     //app_ref_ack             := unconnected
 110     //app_zq_ack              := unconnected
 111
 112     //if(bits(37)==1) {  (upper address range)
 113     // axiaddress = least sig 37 bits of address
 114     //else{ (low address range)
 115     // axiaddress = address ^ 0x8000000
 116     //}
 117
 118     val awaddr = axi_async.aw.bits.addr;
 119     val awbit31 = awaddr(37) & awaddr(31)
 120
 121     val araddr = axi_async.ar.bits.addr;
 122     val arbit31 = araddr(37) & araddr(31)
 123
 124     //slave AXI interface write address ports
 125     blackbox.io.s_axi_awid    := axi_async.aw.bits.id
 126     blackbox.io.s_axi_awaddr  := awaddr //truncated
 127     blackbox.io.s_axi_awlen   := axi_async.aw.bits.len
 128     blackbox.io.s_axi_awsize  := axi_async.aw.bits.size
 129     blackbox.io.s_axi_awburst := axi_async.aw.bits.burst
 130     blackbox.io.s_axi_awlock  := axi_async.aw.bits.lock
 131     blackbox.io.s_axi_awcache := UInt("b0011")
 132     blackbox.io.s_axi_awprot  := axi_async.aw.bits.prot
 133     blackbox.io.s_axi_awqos   := axi_async.aw.bits.qos
 134     blackbox.io.s_axi_awvalid := axi_async.aw.valid
 135     axi_async.aw.ready        := blackbox.io.s_axi_awready
 136
 137     //slave interface write data ports
 138     blackbox.io.s_axi_wdata   := axi_async.w.bits.data
 139     blackbox.io.s_axi_wstrb   := axi_async.w.bits.strb
 140     blackbox.io.s_axi_wlast   := axi_async.w.bits.last
 141     blackbox.io.s_axi_wvalid  := axi_async.w.valid
 142     axi_async.w.ready         := blackbox.io.s_axi_wready
 143
 144     //slave interface write response
 145     blackbox.io.s_axi_bready  := axi_async.b.ready
 146     axi_async.b.bits.id       := blackbox.io.s_axi_bid
 147     axi_async.b.bits.resp     := blackbox.io.s_axi_bresp
 148     axi_async.b.valid         := blackbox.io.s_axi_bvalid
 149
 150     //slave AXI interface read address ports
 151     blackbox.io.s_axi_arid    := axi_async.ar.bits.id
 152     blackbox.io.s_axi_araddr  := araddr // truncated
 153     blackbox.io.s_axi_arlen   := axi_async.ar.bits.len
 154     blackbox.io.s_axi_arsize  := axi_async.ar.bits.size
 155     blackbox.io.s_axi_arburst := axi_async.ar.bits.burst
 156     blackbox.io.s_axi_arlock  := axi_async.ar.bits.lock
 157     blackbox.io.s_axi_arcache := UInt("b0011")
 158     blackbox.io.s_axi_arprot  := axi_async.ar.bits.prot
 159     blackbox.io.s_axi_arqos   := axi_async.ar.bits.qos
 160     blackbox.io.s_axi_arvalid := axi_async.ar.valid
 161     axi_async.ar.ready        := blackbox.io.s_axi_arready
 162
 163     //slace AXI interface read data ports
 164     blackbox.io.s_axi_rready  := axi_async.r.ready
 165     axi_async.r.bits.id       := blackbox.io.s_axi_rid
 166     axi_async.r.bits.data     := blackbox.io.s_axi_rdata
 167     axi_async.r.bits.resp     := blackbox.io.s_axi_rresp
 168     axi_async.r.bits.last     := blackbox.io.s_axi_rlast
 169     axi_async.r.valid         := blackbox.io.s_axi_rvalid
 170
 171     //misc
 172     io.port.init_calib_complete := blackbox.io.init_calib_complete
 173     blackbox.io.sys_rst       :=io.port.sys_rst
 174     //mig.device_temp         :- unconnceted
 175   }
 176 }