1 // See LICENSE for license details.
2 package sifive.blocks.devices.xilinxvc707mig
5 import freechips.rocketchip.config._
6 import freechips.rocketchip.coreplex.HasMemoryBus
7 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
9 case object MemoryXilinxDDRKey extends Field[XilinxVC707MIGParams]
11 trait HasMemoryXilinxVC707MIG extends HasMemoryBus {
12 val module: HasMemoryXilinxVC707MIGModuleImp
14 val xilinxvc707mig = LazyModule(new XilinxVC707MIG(p(MemoryXilinxDDRKey)))
16 require(nMemoryChannels == 1, "Coreplex must have 1 master memory port")
17 xilinxvc707mig.node := memBuses.head.toDRAMController
20 trait HasMemoryXilinxVC707MIGBundle {
21 val xilinxvc707mig: XilinxVC707MIGIO
22 def connectXilinxVC707MIGToPads(pads: XilinxVC707MIGPads) {
23 pads <> xilinxvc707mig
27 trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
28 with HasMemoryXilinxVC707MIGBundle {
29 val outer: HasMemoryXilinxVC707MIG
30 val xilinxvc707mig = IO(new XilinxVC707MIGIO(p(MemoryXilinxDDRKey).depthGB))
32 xilinxvc707mig <> outer.xilinxvc707mig.module.io.port