src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.xilinxvc707mig
   3
   4 import Chisel._
   5 import diplomacy._
   6 import rocketchip.{
   7   HasTopLevelNetworks,
   8   HasTopLevelNetworksModule,
   9   HasTopLevelNetworksBundle
  10 }
  11 import coreplex.BankedL2Config
  12
  13 trait HasPeripheryXilinxVC707MIG extends HasTopLevelNetworks {
  14   val module: HasPeripheryXilinxVC707MIGModule
  15
  16   val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
  17   require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
  18   xilinxvc707mig.node := mem(0).node
  19 }
  20
  21 trait HasPeripheryXilinxVC707MIGBundle extends HasTopLevelNetworksBundle {
  22   val xilinxvc707mig = new XilinxVC707MIGIO
  23 }
  24
  25 trait HasPeripheryXilinxVC707MIGModule extends HasTopLevelNetworksModule {
  26   val outer: HasPeripheryXilinxVC707MIG
  27   val io: HasPeripheryXilinxVC707MIGBundle
  28
  29   io.xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
  30 }