src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.xilinxvc707mig
   3
   4 import Chisel._
   5 import freechips.rocketchip.config._
   6 import freechips.rocketchip.coreplex.HasMemoryBus
   7 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp, AddressRange}
   8
   9 case object MemoryXilinxDDRKey extends Field[XilinxVC707MIGParams]
  10
  11 trait HasMemoryXilinxVC707MIG extends HasMemoryBus {
  12   val module: HasMemoryXilinxVC707MIGModuleImp
  13
  14   val xilinxvc707mig = LazyModule(new XilinxVC707MIG(p(MemoryXilinxDDRKey)))
  15
  16   require(nMemoryChannels == 1, "Coreplex must have 1 master memory port")
  17   xilinxvc707mig.node := memBuses.head.toDRAMController
  18 }
  19
  20 trait HasMemoryXilinxVC707MIGBundle {
  21   val xilinxvc707mig: XilinxVC707MIGIO
  22   def connectXilinxVC707MIGToPads(pads: XilinxVC707MIGPads) {
  23     pads <> xilinxvc707mig
  24   }
  25 }
  26
  27 trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
  28     with HasMemoryXilinxVC707MIGBundle {
  29   val outer: HasMemoryXilinxVC707MIG
  30   val ranges = AddressRange.fromSets(p(MemoryXilinxDDRKey).address)
  31   require (ranges.size == 1, "DDR range must be contiguous")
  32   val depth = ranges.head.size
  33   val xilinxvc707mig = IO(new XilinxVC707MIGIO(depth))
  34
  35   xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
  36 }