src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.xilinxvc707pciex1
   3
   4 import Chisel._
   5 import config._
   6 import diplomacy._
   7 import uncore.tilelink2._
   8 import uncore.axi4._
   9 import rocketchip._
  10 import sifive.blocks.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial}
  11 import sifive.blocks.ip.xilinx.ibufds_gte2.IBUFDS_GTE2
  12
  13 class XilinxVC707PCIeX1Pads extends Bundle with VC707AXIToPCIeX1IOSerial
  14
  15 class XilinxVC707PCIeX1IO extends Bundle with VC707AXIToPCIeX1IOSerial
  16                                          with VC707AXIToPCIeX1IOClocksReset {
  17   val axi_ctl_aresetn = Bool(INPUT)
  18   val REFCLK_rxp = Bool(INPUT)
  19   val REFCLK_rxn = Bool(INPUT)
  20 }
  21
  22 class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
  23   val slave = TLInputNode()
  24   val control = TLInputNode()
  25   val master = TLOutputNode()
  26   val intnode = IntOutputNode()
  27
  28   val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
  29
  30   axi_to_pcie_x1.slave :=
  31     AXI4Buffer()(
  32     AXI4UserYanker()(
  33     AXI4Deinterleaver(p(coreplex.CacheBlockBytes))(
  34     AXI4IdIndexer(idBits=4)(
  35     TLToAXI4(beatBytes=8)(
  36     slave)))))
  37
  38   axi_to_pcie_x1.control :=
  39     AXI4Buffer()(
  40     AXI4UserYanker()(
  41     TLToAXI4(beatBytes=4)(
  42     TLFragmenter(4, p(coreplex.CacheBlockBytes))(
  43     control))))
  44
  45   master :=
  46     TLWidthWidget(8)(
  47     AXI4ToTL()(
  48     AXI4UserYanker(capMaxFlight=Some(8))(
  49     AXI4Fragmenter()(
  50     axi_to_pcie_x1.master))))
  51
  52   intnode := axi_to_pcie_x1.intnode
  53
  54   lazy val module = new LazyModuleImp(this) {
  55     val io = new Bundle {
  56       val port = new XilinxVC707PCIeX1IO
  57       val slave_in = slave.bundleIn
  58       val control_in = control.bundleIn
  59       val master_out = master.bundleOut
  60       val interrupt = intnode.bundleOut
  61     }
  62
  63     io.port <> axi_to_pcie_x1.module.io.port
  64
  65     //PCIe Reference Clock
  66     val ibufds_gte2 = Module(new IBUFDS_GTE2)
  67     axi_to_pcie_x1.module.io.REFCLK := ibufds_gte2.io.O
  68     ibufds_gte2.io.CEB := UInt(0)
  69     ibufds_gte2.io.I := io.port.REFCLK_rxp
  70     ibufds_gte2.io.IB := io.port.REFCLK_rxn
  71   }
  72 }