src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.xilinxvc707pciex1
   3
   4 import Chisel._
   5 import diplomacy.LazyModule
   6 import rocketchip.{
   7   HasTopLevelNetworks,
   8   HasTopLevelNetworksModule,
   9   HasTopLevelNetworksBundle
  10 }
  11 import uncore.tilelink2.TLWidthWidget
  12
  13 trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
  14
  15   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
  16   fsb.node := xilinxvc707pcie.master
  17   xilinxvc707pcie.slave   := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
  18   xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
  19   intBus.intnode := xilinxvc707pcie.intnode
  20 }
  21
  22 trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
  23   val xilinxvc707pcie = new XilinxVC707PCIeX1IO
  24 }
  25
  26 trait HasPeripheryXilinxVC707PCIeX1Module extends HasTopLevelNetworksModule {
  27   val outer: HasPeripheryXilinxVC707PCIeX1
  28   val io: HasPeripheryXilinxVC707PCIeX1Bundle
  29
  30   io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
  31 }