src/main/scala/ip/xilinx/vc707mig/vc707mig.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.ip.xilinx.vc707mig
   3
   4 import Chisel._
   5 import chisel3.experimental.{Analog,attach}
   6 import freechips.rocketchip.util.GenericParameterizedBundle
   7 import freechips.rocketchip.config._
   8
   9 // IP VLNV: xilinx.com:customize_ip:vc707mig:1.0
  10 // Black Box
  11
  12 class VC707MIGIODDR(depth : BigInt) extends GenericParameterizedBundle(depth) {
  13   require((depth==0x40000000L) || (depth==0x100000000L),"VC707MIGIODDR supports 1GB and 4GB depth configuraton only")
  14   val ddr3_addr             = Bits(OUTPUT,if(depth==0x40000000L) 14 else 16)
  15   val ddr3_ba               = Bits(OUTPUT,3)
  16   val ddr3_ras_n            = Bool(OUTPUT)
  17   val ddr3_cas_n            = Bool(OUTPUT)
  18   val ddr3_we_n             = Bool(OUTPUT)
  19   val ddr3_reset_n          = Bool(OUTPUT)
  20   val ddr3_ck_p             = Bits(OUTPUT,1)
  21   val ddr3_ck_n             = Bits(OUTPUT,1)
  22   val ddr3_cke              = Bits(OUTPUT,1)
  23   val ddr3_cs_n             = Bits(OUTPUT,1)
  24   val ddr3_dm               = Bits(OUTPUT,8)
  25   val ddr3_odt              = Bits(OUTPUT,1)
  26
  27   val ddr3_dq               = Analog(64.W)
  28   val ddr3_dqs_n            = Analog(8.W)
  29   val ddr3_dqs_p            = Analog(8.W)
  30 }
  31
  32 //reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig
  33 trait VC707MIGIOClocksReset extends Bundle {
  34   //inputs
  35   //"NO_BUFFER" clock source (must be connected to IBUF outside of IP)
  36   val sys_clk_i             = Bool(INPUT)
  37   //user interface signals
  38   val ui_clk                = Clock(OUTPUT)
  39   val ui_clk_sync_rst       = Bool(OUTPUT)
  40   val mmcm_locked           = Bool(OUTPUT)
  41   val aresetn               = Bool(INPUT)
  42   //misc
  43   val init_calib_complete   = Bool(OUTPUT)
  44   val sys_rst               = Bool(INPUT)
  45 }
  46
  47 //scalastyle:off
  48 //turn off linter: blackbox name must match verilog module
  49 class vc707mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox
  50 {
  51   private val oneGB  : BigInt = 0x40000000L
  52   private val fourGB : BigInt = 0x100000000L
  53   require((depth==oneGB) || (depth==fourGB),"vc707mig supports 1GB and 4GB depth configuraton only")
  54
  55   override def desiredName = if(depth==fourGB) "vc707mig4gb" else "vc707mig"
  56
  57   val io = new VC707MIGIODDR(depth) with VC707MIGIOClocksReset {
  58     // User interface signals
  59     val app_sr_req            = Bool(INPUT)
  60     val app_ref_req           = Bool(INPUT)
  61     val app_zq_req            = Bool(INPUT)
  62     val app_sr_active         = Bool(OUTPUT)
  63     val app_ref_ack           = Bool(OUTPUT)
  64     val app_zq_ack            = Bool(OUTPUT)
  65     //axi_s
  66     //slave interface write address ports
  67     val s_axi_awid            = Bits(INPUT,4)
  68     val s_axi_awaddr          = Bits(INPUT,if(depth==oneGB) 30 else 32)
  69     val s_axi_awlen           = Bits(INPUT,8)
  70     val s_axi_awsize          = Bits(INPUT,3)
  71     val s_axi_awburst         = Bits(INPUT,2)
  72     val s_axi_awlock          = Bits(INPUT,1)
  73     val s_axi_awcache         = Bits(INPUT,4)
  74     val s_axi_awprot          = Bits(INPUT,3)
  75     val s_axi_awqos           = Bits(INPUT,4)
  76     val s_axi_awvalid         = Bool(INPUT)
  77     val s_axi_awready         = Bool(OUTPUT)
  78     //slave interface write data ports
  79     val s_axi_wdata           = Bits(INPUT,64)
  80     val s_axi_wstrb           = Bits(INPUT,8)
  81     val s_axi_wlast           = Bool(INPUT)
  82     val s_axi_wvalid          = Bool(INPUT)
  83     val s_axi_wready          = Bool(OUTPUT)
  84     //slave interface write response ports
  85     val s_axi_bready          = Bool(INPUT)
  86     val s_axi_bid             = Bits(OUTPUT,4)
  87     val s_axi_bresp           = Bits(OUTPUT,2)
  88     val s_axi_bvalid          = Bool(OUTPUT)
  89     //slave interface read address ports
  90     val s_axi_arid            = Bits(INPUT,4)
  91     val s_axi_araddr          = Bits(INPUT,if(depth==oneGB) 30 else 32)
  92     val s_axi_arlen           = Bits(INPUT,8)
  93     val s_axi_arsize          = Bits(INPUT,3)
  94     val s_axi_arburst         = Bits(INPUT,2)
  95     val s_axi_arlock          = Bits(INPUT,1)
  96     val s_axi_arcache         = Bits(INPUT,4)
  97     val s_axi_arprot          = Bits(INPUT,3)
  98     val s_axi_arqos           = Bits(INPUT,4)
  99     val s_axi_arvalid         = Bool(INPUT)
 100     val s_axi_arready         = Bool(OUTPUT)
 101     //slave interface read data ports
 102     val s_axi_rready          = Bool(INPUT)
 103     val s_axi_rid             = Bits(OUTPUT,4)
 104     val s_axi_rdata           = Bits(OUTPUT,64)
 105     val s_axi_rresp           = Bits(OUTPUT,2)
 106     val s_axi_rlast           = Bool(OUTPUT)
 107     val s_axi_rvalid          = Bool(OUTPUT)
 108     //misc
 109     val device_temp           = Bits(OUTPUT,12)
 110   }
 111 }
 112 //scalastyle:on