vsrc/vc707reset.v

   1 // See LICENSE for license details.
   2 `timescale 1ns/1ps
   3 `default_nettype none
   4 `define RESET_SYNC 4
   5 `define DEBOUNCE_BITS 8
   6
   7 module vc707reset(
   8   // Asynchronous reset input, should be held high until
   9   // all clocks are locked and power is stable.
  10   input  wire areset,
  11   // Clock domains are brought up in increasing order
  12   // All clocks are reset for at least 2^DEBOUNCE_BITS * period(clock1)
  13   input  wire clock1,
  14   output wire reset1,
  15   input  wire clock2,
  16   output wire reset2,
  17   input  wire clock3,
  18   output wire reset3,
  19   input  wire clock4,
  20   output wire reset4
  21 );
  22   sifive_reset_hold hold_clock0(areset, clock1, reset1);
  23   sifive_reset_sync sync_clock2(reset1, clock2, reset2);
  24   sifive_reset_sync sync_clock3(reset2, clock3, reset3);
  25   sifive_reset_sync sync_clock4(reset3, clock4, reset4);
  26 endmodule
  27
  28 // Assumes that areset is held for more than one clock
  29 // Allows areset to be deasserted asynchronously
  30 module sifive_reset_sync(
  31   input  wire areset,
  32   input  wire clock,
  33   output wire reset
  34 );
  35   reg [`RESET_SYNC-1:0] gen_reset = {`RESET_SYNC{1'b1}};
  36   always @(posedge clock, posedge areset) begin
  37     if (areset) begin
  38       gen_reset <= {`RESET_SYNC{1'b1}};
  39     end else begin
  40       gen_reset <= {1'b0,gen_reset[`RESET_SYNC-1:1]};
  41     end
  42   end
  43   assign reset = gen_reset[0];
  44 endmodule
  45
  46 module sifive_reset_hold(
  47   input  wire areset,
  48   input  wire clock,
  49   output wire reset
  50 );
  51   wire raw_reset;
  52   reg [`RESET_SYNC-1:0] sync_reset = {`RESET_SYNC{1'b1}};
  53   reg [`DEBOUNCE_BITS:0] debounce_reset = {`DEBOUNCE_BITS{1'b1}};
  54   wire out_reset;
  55
  56   // Captures reset even if clock is not running
  57   sifive_reset_sync capture(areset, clock, raw_reset);
  58
  59   // Remove any glitches due to runt areset
  60   always @(posedge clock) begin
  61     sync_reset <= {raw_reset,sync_reset[`RESET_SYNC-1:1]};
  62   end
  63
  64   // Debounce the reset
  65   assign out_reset = debounce_reset[`DEBOUNCE_BITS];
  66   always @(posedge clock) begin
  67     if (sync_reset[0]) begin
  68       debounce_reset <= {(`DEBOUNCE_BITS+1){1'b1}};
  69     end else begin
  70       debounce_reset <= debounce_reset - out_reset;
  71     end
  72   end
  73
  74   assign reset = out_reset;
  75
  76 endmodule
  77
  78 `default_nettype wire