import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
-import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
case object PeripheryI2CKey extends Field[Seq[I2CParams]]
}
trait HasPeripheryI2CBundle {
- val i2cs: Vec[I2CPort]
-
- def I2CtoGPIOPins(syncStages: Int = 0): Seq[I2CPinsIO] = i2cs.map { i =>
- val pins = Module(new I2CGPIOPort(syncStages))
- pins.io.i2c <> i
- pins.io.pins
- }
+ val i2c: Vec[I2CPort]
}
-trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle {
+trait HasPeripheryI2CModuleImp extends LazyModuleImp with HasPeripheryI2CBundle {
val outer: HasPeripheryI2C
- val i2cs = IO(Vec(outer.i2cParams.size, new I2CPort))
+ val i2c = IO(Vec(outer.i2cParams.size, new I2CPort))
- (i2cs zip outer.i2c).foreach { case (io, device) =>
+ (i2c zip outer.i2c).foreach { case (io, device) =>
io <> device.module.io.port
}
}