shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate

[sifive-blocks.git] / src / main / scala / devices / i2c / I2CPins.scala

diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala
index 9bbc57605dd2ca6976912328659d99192ba5cf61..6bf40aedd5526975ebfd5fe7ecb186b643927c09 100644 (file)
--- a/src/main/scala/devices/i2c/I2CPins.scala
+++ b/src/main/scala/devices/i2c/I2CPins.scala
@@ -3,7 +3,7 @@ package sifive.blocks.devices.i2c
 
 import Chisel._
 import chisel3.experimental.{withClockAndReset}
-import freechips.rocketchip.util.SynchronizerShiftRegInit
+import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
 import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
 
 class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
@@ -18,12 +18,12 @@ class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
     withClockAndReset(clock, reset) {
       scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
       scl.o.oe := i2c.scl.oe
-      i2c.scl.in := SynchronizerShiftRegInit(scl.i.ival, syncStages, init = Bool(true),
+      i2c.scl.in := SyncResetSynchronizerShiftReg(scl.i.ival, syncStages, init = Bool(true),
         name = Some("i2c_scl_sync"))
 
       sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
       sda.o.oe := i2c.sda.oe
-      i2c.sda.in := SynchronizerShiftRegInit(sda.i.ival, syncStages, init = Bool(true),
+      i2c.sda.in := SyncResetSynchronizerShiftReg(sda.i.ival, syncStages, init = Bool(true),
         name = Some("i2c_sda_sync"))
     }
   }