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GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they...
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
uart
/
UARTPeriphery.scala
diff --git
a/src/main/scala/devices/uart/UARTPeriphery.scala
b/src/main/scala/devices/uart/UARTPeriphery.scala
index a0e83ffffed8515b5ca546070a8ea3c18bc0db50..05c4a33890e13280f646b40cd5f242ad599f82b6 100644
(file)
--- a/
src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/
src/main/scala/devices/uart/UARTPeriphery.scala
@@
-29,8
+29,8
@@
trait HasPeripheryUARTBundle {
uarts.foreach { _.rxd := UInt(1) }
}
uarts.foreach { _.rxd := UInt(1) }
}
- def UARTtoGPIOPins(
dummy: Int = 1
): Seq[UARTGPIOPort] = uarts.map { u =>
- val pin = Module(new UARTGPIOPort)
+ def UARTtoGPIOPins(
sync_stages: Int = 0
): Seq[UARTGPIOPort] = uarts.map { u =>
+ val pin = Module(new UARTGPIOPort
(sync_stages)
)
pin.io.uart <> u
pin
}
pin.io.uart <> u
pin
}