GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they...
[sifive-blocks.git] / src / main / scala / devices / uart /
drwxr-xr-x   ..
-rw-r--r-- 7121 UART.scala
-rw-r--r-- 277 UARTCtrlRegs.scala
-rw-r--r-- 1737 UARTPeriphery.scala