Refactor package hierarchy. (#25)

[sifive-blocks.git] / src / main / scala / devices / xilinxvc707mig / XilinxVC707MIGPeriphery.scala

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
index bf187ff1ef15834abab712ee7038b79a6987d91b..540821ecc4b336e90ede107e73851cd088b2edce 100644 (file)
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
@@ -2,8 +2,8 @@
 package sifive.blocks.devices.xilinxvc707mig
 
 import Chisel._
-import diplomacy.{LazyModule, LazyMultiIOModuleImp}
-import rocketchip.HasSystemNetworks
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
 
 trait HasPeripheryXilinxVC707MIG extends HasSystemNetworks {
   val module: HasPeripheryXilinxVC707MIGModuleImp