Refactor package hierarchy. (#25)

[sifive-blocks.git] / src / main / scala / ip / xilinx / vc707mig / vc707mig.scala

diff --git a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
index d7b522fd7eaa0ab38c7a67638387353fe60ddeb5..1e01748b531eac309e5f3087149ca1fee2619587 100644 (file)
--- a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
+++ b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
@@ -3,8 +3,7 @@ package sifive.blocks.ip.xilinx.vc707mig
 
 import Chisel._
 import chisel3.experimental.{Analog,attach}
-import config._
-import junctions._
+import freechips.rocketchip.config._
 
 // IP VLNV: xilinx.com:customize_ip:vc707mig:1.0
 // Black Box