Refactor package hierarchy. (#25)

[sifive-blocks.git] / src / main / scala / util / ResetCatchAndSync.scala

diff --git a/src/main/scala/util/ResetCatchAndSync.scala b/src/main/scala/util/ResetCatchAndSync.scala
index cc35686cc249a5d019422c64cb1b40a1a17cb33e..6b483e53a2cce3dde7691545f56213684a0399c3 100644 (file)
--- a/src/main/scala/util/ResetCatchAndSync.scala
+++ b/src/main/scala/util/ResetCatchAndSync.scala
@@ -2,7 +2,7 @@
 package sifive.blocks.util
 
 import Chisel._
-import util.AsyncResetRegVec
+import freechips.rocketchip.util.AsyncResetRegVec
 
 /** Reset: asynchronous assert,
   *  synchronous de-assert