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gpio: Use Synchronizer for the inputs
author
Megan Wachs
<megan@sifive.com>
Wed, 6 Sep 2017 01:35:09 +0000
(18:35 -0700)
committer
Megan Wachs
<megan@sifive.com>
Wed, 6 Sep 2017 01:35:09 +0000
(18:35 -0700)
src/main/scala/devices/gpio/GPIO.scala
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diff --git
a/src/main/scala/devices/gpio/GPIO.scala
b/src/main/scala/devices/gpio/GPIO.scala
index 2bb04fe2a53a3760ebd047ef24495ef07956298d..d4cd24e07d58541f1b6a08fa88cdb907072485e9 100644
(file)
--- a/
src/main/scala/devices/gpio/GPIO.scala
+++ b/
src/main/scala/devices/gpio/GPIO.scala
@@
-4,6
+4,7
@@
package sifive.blocks.devices.gpio
import Chisel._
import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl}
import freechips.rocketchip.config.Parameters
import Chisel._
import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl}
import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.util.SynchronizerShiftReg
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
@@
-106,7
+107,7
@@
trait HasGPIOModuleContents extends Module with HasRegMap {
// Synchronize Input to get valueReg
val inVal = Wire(UInt(0, width=c.width))
inVal := Vec(io.port.pins.map(_.i.ival)).asUInt
// Synchronize Input to get valueReg
val inVal = Wire(UInt(0, width=c.width))
inVal := Vec(io.port.pins.map(_.i.ival)).asUInt
- val inSyncReg = S
hiftRegister(inVal, 3
)
+ val inSyncReg = S
ynchronizerShiftReg(inVal, 3, Some("inSyncReg")
)
val valueReg = Reg(init = UInt(0, c.width), next = inSyncReg)
// Interrupt Configuration
val valueReg = Reg(init = UInt(0, c.width), next = inSyncReg)
// Interrupt Configuration