wip

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index 48dedbc41e8f5ebbb4102292efb2a579681db317..6776b2eaa69427e81e5e2ba09fce686fccb55d2d 100644 (file)
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -11,8 +11,7 @@ import freechips.rocketchip.tilelink._
 import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
 
 case class XilinxVC707MIGParams(
-  address : Seq[AddressSet],
-  depthGB : Int
+  depthGB : Int 
 )
 
 class XilinxVC707MIGPads(depthGB : Integer) extends VC707MIGIODDR(depthGB)
@@ -20,18 +19,18 @@ class XilinxVC707MIGPads(depthGB : Integer) extends VC707MIGIODDR(depthGB)
 class XilinxVC707MIGIO(depthGB : Integer) extends VC707MIGIODDR(depthGB) with VC707MIGIOClocksReset
 
 class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule {
-  // Supported depth configurations
-  require((c.depthGB==1) || (c.depthGB==4),"XilinxVC707MIG supports 1GB and 4GB depth configuraton only")
+  require((c.depthGB == 1) || (c.depthGB == 4))
+
   // Suppoted address map configuratons
-  if(c.depthGB==1) require(c.address == Seq(AddressSet(0x80000000L ,  0x80000000L-1)))   //2GB   @ 2GB
-  if(c.depthGB==4) require(c.address == Seq(AddressSet(0x80000000L,   0x80000000L-1),    //2GB   @ 2GB
-                                            AddressSet(0x2080000000L, 0x80000000L-1)))   //2GB   @ 130GB
+  val address = if(c.depthGB == 1) Seq(AddressSet(0x80000000L ,  0x80000000L-1))       //2GB   @ 2GB
+                else Seq(AddressSet(0x80000000L,   0x80000000L-1),       //2GB   @ 2GB
+                         AddressSet(0x2080000000L, 0x80000000L-1))       //2GB   @ 130GB
   
   val device = new MemoryDevice
   val node = TLInputNode()
   val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
       slaves = Seq(AXI4SlaveParameters(
-      address       = c.address,
+      address       = address,
       resources     = device.reg,
       regionType    = RegionType.UNCACHED,
       executable    = true,

diff --git a/src/main/scala/ip/xilinx/vc707mig/vc707mig4gb.scala b/src/main/scala/ip/xilinx/vc707mig/vc707mig4gb.scala
deleted file mode 100644 (file)
index 7f05187..0000000
--- a/src/main/scala/ip/xilinx/vc707mig/vc707mig4gb.scala
+++ /dev/null
@@ -1,105 +0,0 @@
-// See LICENSE for license details.
-package sifive.blocks.ip.xilinx.vc707mig4gb
-
-import Chisel._
-import chisel3.experimental.{Analog,attach}
-import freechips.rocketchip.config._
-
-// IP VLNV: xilinx.com:customize_ip:vc707mig:1.0
-// Black Box
-
-trait VC707MIG4GBIODDR extends Bundle {
-  val ddr3_addr             = Bits(OUTPUT,16)
-  val ddr3_ba               = Bits(OUTPUT,3)
-  val ddr3_ras_n            = Bool(OUTPUT)
-  val ddr3_cas_n            = Bool(OUTPUT)
-  val ddr3_we_n             = Bool(OUTPUT)
-  val ddr3_reset_n          = Bool(OUTPUT)
-  val ddr3_ck_p             = Bits(OUTPUT,1)
-  val ddr3_ck_n             = Bits(OUTPUT,1)
-  val ddr3_cke              = Bits(OUTPUT,1)
-  val ddr3_cs_n             = Bits(OUTPUT,1)
-  val ddr3_dm               = Bits(OUTPUT,8)
-  val ddr3_odt              = Bits(OUTPUT,1)
-
-  val ddr3_dq               = Analog(64.W)
-  val ddr3_dqs_n            = Analog(8.W)
-  val ddr3_dqs_p            = Analog(8.W)
-}
-
-//reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig
-trait VC707MIG4GBIOClocksReset extends Bundle {
-  //inputs
-  //"NO_BUFFER" clock source (must be connected to IBUF outside of IP)
-  val sys_clk_i             = Bool(INPUT)
-  //user interface signals
-  val ui_clk                = Clock(OUTPUT)
-  val ui_clk_sync_rst       = Bool(OUTPUT)
-  val mmcm_locked           = Bool(OUTPUT)
-  val aresetn               = Bool(INPUT)
-  //misc
-  val init_calib_complete   = Bool(OUTPUT)
-  val sys_rst               = Bool(INPUT)
-}
-
-//scalastyle:off
-//turn off linter: blackbox name must match verilog module 
-class vc707mig4gb(implicit val p:Parameters) extends BlackBox
-{
-  val io = new Bundle with VC707MIG4GBIODDR
-                      with VC707MIG4GBIOClocksReset {
-    // User interface signals
-    val app_sr_req            = Bool(INPUT)
-    val app_ref_req           = Bool(INPUT)
-    val app_zq_req            = Bool(INPUT)
-    val app_sr_active         = Bool(OUTPUT)
-    val app_ref_ack           = Bool(OUTPUT)
-    val app_zq_ack            = Bool(OUTPUT)
-    //axi_s
-    //slave interface write address ports
-    val s_axi_awid            = Bits(INPUT,4)
-    val s_axi_awaddr          = Bits(INPUT,32)
-    val s_axi_awlen           = Bits(INPUT,8)
-    val s_axi_awsize          = Bits(INPUT,3)
-    val s_axi_awburst         = Bits(INPUT,2)
-    val s_axi_awlock          = Bits(INPUT,1)
-    val s_axi_awcache         = Bits(INPUT,4)
-    val s_axi_awprot          = Bits(INPUT,3)
-    val s_axi_awqos           = Bits(INPUT,4)
-    val s_axi_awvalid         = Bool(INPUT)
-    val s_axi_awready         = Bool(OUTPUT)
-    //slave interface write data ports
-    val s_axi_wdata           = Bits(INPUT,64)
-    val s_axi_wstrb           = Bits(INPUT,8)
-    val s_axi_wlast           = Bool(INPUT)
-    val s_axi_wvalid          = Bool(INPUT)
-    val s_axi_wready          = Bool(OUTPUT)
-    //slave interface write response ports
-    val s_axi_bready          = Bool(INPUT)
-    val s_axi_bid             = Bits(OUTPUT,4)
-    val s_axi_bresp           = Bits(OUTPUT,2)
-    val s_axi_bvalid          = Bool(OUTPUT)
-    //slave interface read address ports
-    val s_axi_arid            = Bits(INPUT,4)
-    val s_axi_araddr          = Bits(INPUT,32)
-    val s_axi_arlen           = Bits(INPUT,8)
-    val s_axi_arsize          = Bits(INPUT,3)
-    val s_axi_arburst         = Bits(INPUT,2)
-    val s_axi_arlock          = Bits(INPUT,1)
-    val s_axi_arcache         = Bits(INPUT,4)
-    val s_axi_arprot          = Bits(INPUT,3)
-    val s_axi_arqos           = Bits(INPUT,4)
-    val s_axi_arvalid         = Bool(INPUT)
-    val s_axi_arready         = Bool(OUTPUT)
-    //slave interface read data ports
-    val s_axi_rready          = Bool(INPUT)
-    val s_axi_rid             = Bits(OUTPUT,4)
-    val s_axi_rdata           = Bits(OUTPUT,64)
-    val s_axi_rresp           = Bits(OUTPUT,2)
-    val s_axi_rlast           = Bool(OUTPUT)
-    val s_axi_rvalid          = Bool(OUTPUT)
-    //misc
-    val device_temp           = Bits(OUTPUT,12)
-  }
-}
-//scalastyle:on