Merge remote-tracking branch 'origin/master' into i2c

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index 992699fa6c907e949a3e168eb7913787ed02b0bd..86e9ad2f3f8756aca2db7300190f28131faf0497 100644 (file)
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -30,8 +30,8 @@ class PWMGPIOPort(c: PWMBundleConfig)(implicit p: Parameters) extends Module {
 trait PeripheryPWM {
   this: TopNetwork { val pwmConfigs: Seq[PWMConfig] } =>
 
-  val pwmDevices = (pwmConfigs.zipWithIndex) map { case (c, i) =>
-    val pwm = LazyModule(new TLPWM(c) { override lazy val  valName = Some(s"pwm$i") })
+  val pwm = (pwmConfigs.zipWithIndex) map { case (c, i) =>
+    val pwm = LazyModule(new TLPWM(c))
     pwm.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := pwm.intnode
     pwm
@@ -52,7 +52,7 @@ trait PeripheryPWMModule {
     val outer: PeripheryPWM
     val io: PeripheryPWMBundle
   } =>
-  (io.pwms.zipWithIndex zip outer.pwmDevices) foreach { case ((io, i), device) =>
+  (io.pwms.zipWithIndex zip outer.pwm) foreach { case ((io, i), device) =>
     io.port := device.module.io.gpio
   }
 }

diff --git a/src/main/scala/devices/spi/SPIConsts.scala b/src/main/scala/devices/spi/SPIConsts.scala
index b18b08a4acbaaed701253505d97fda22c8d1fb69..5d6dd0d15c0e4a0e24d1f2f2bfa9d4539ce2be09 100644 (file)
--- a/src/main/scala/devices/spi/SPIConsts.scala
+++ b/src/main/scala/devices/spi/SPIConsts.scala
@@ -5,29 +5,29 @@ import Chisel._
 
 object SPIProtocol {
   val width = 2
-  val Single = UInt(0, width)
-  val Dual   = UInt(1, width)
-  val Quad   = UInt(2, width)
+  def Single = UInt(0, width)
+  def Dual   = UInt(1, width)
+  def Quad   = UInt(2, width)
 
-  val cases = Seq(Single, Dual, Quad)
+  def cases = Seq(Single, Dual, Quad)
   def decode(x: UInt): Seq[Bool] = cases.map(_ === x)
 }
 
 object SPIDirection {
   val width = 1
-  val Rx = UInt(0, width)
-  val Tx = UInt(1, width)
+  def Rx = UInt(0, width)
+  def Tx = UInt(1, width)
 }
 
 object SPIEndian {
   val width = 1
-  val MSB = UInt(0, width)
-  val LSB = UInt(1, width)
+  def MSB = UInt(0, width)
+  def LSB = UInt(1, width)
 }
 
 object SPICSMode {
   val width = 2
-  val Auto = UInt(0, width)
-  val Hold = UInt(2, width)
-  val Off  = UInt(3, width)
+  def Auto = UInt(0, width)
+  def Hold = UInt(2, width)
+  def Off  = UInt(3, width)
 }

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index 40bcec692f9265f5b9fa590a09a060194244ff23..f4773a228c7cabf9646381ed4b9cea756be77270 100644 (file)
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -8,8 +8,8 @@ import rocketchip.{TopNetwork,TopNetworkModule}
 
 trait PeripherySPI {
   this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
-  val spiDevices = (spiConfigs.zipWithIndex) map {case (c, i) =>
-    val spi = LazyModule(new TLSPI(c) { override lazy val valName = Some(s"spi$i") } )
+  val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
+    val spi = LazyModule(new TLSPI(c))
     spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := spi.intnode
     spi
@@ -28,7 +28,7 @@ trait PeripherySPIModule {
     val outer: PeripherySPI
     val io: PeripherySPIBundle
   } =>
-  (io.spis zip outer.spiDevices).foreach { case (io, device) =>
+  (io.spis zip outer.spi).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }

diff --git a/src/main/scala/devices/spi/SPIPhysical.scala b/src/main/scala/devices/spi/SPIPhysical.scala
index 6584be8b0272ccd016eb97fc38e97b44a1ff7f70..cb26bc99046e3dbeb273b376e397b31c611b5567 100644 (file)
--- a/src/main/scala/devices/spi/SPIPhysical.scala
+++ b/src/main/scala/devices/spi/SPIPhysical.scala
@@ -12,8 +12,8 @@ class SPIMicroOp(c: SPIConfigBase) extends SPIBundle(c) {
 }
 
 object SPIMicroOp {
-  val Transfer = UInt(0, 1)
-  val Delay    = UInt(1, 1)
+  def Transfer = UInt(0, 1)
+  def Delay    = UInt(1, 1)
 }
 
 class SPIPhyControl(c: SPIConfigBase) extends SPIBundle(c) {

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index fd5bc35db4838105187197ef82622c31c948a2d1..3639d9baebef5c5ad1e5541e62f1a9e679ae52aa 100644 (file)
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -14,8 +14,8 @@ trait PeripheryUART {
   this: TopNetwork {
     val uartConfigs: Seq[UARTConfig]
   } =>
-  val uartDevices = uartConfigs.zipWithIndex.map { case (c, i) =>
-    val uart = LazyModule(new UART(c) { override lazy val valName = Some(s"uart$i") } )
+  val uart = uartConfigs.zipWithIndex.map { case (c, i) =>
+    val uart = LazyModule(new UART(c))
     uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := uart.intnode
     uart
@@ -32,7 +32,7 @@ trait PeripheryUARTModule {
     val outer: PeripheryUART
     val io: PeripheryUARTBundle
   } =>
-  (io.uarts zip outer.uartDevices).foreach { case (io, device) =>
+  (io.uarts zip outer.uart).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
index b52b37c0e699b99b2e1c453bb9f37e927582100f..4586949c0eada15181f58e5c4186f7118fa87841 100644 (file)
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
@@ -11,7 +11,7 @@ trait PeripheryXilinxVC707MIG extends TopNetwork {
 
   val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
   require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
-  val mem = Seq(xilinxvc707mig.node)
+  xilinxvc707mig.node := mem(0).node
 }
 
 trait PeripheryXilinxVC707MIGBundle extends TopNetworkBundle {

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
index 494d787a791504c4f3b2e9a941b74e677d7134b0..4a64766dbbb719e23e12abb8f515ebf4ebc4f1d6 100644 (file)
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
@@ -3,10 +3,10 @@ package sifive.blocks.devices.xilinxvc707pciex1
 
 import Chisel._
 import diplomacy.LazyModule
-import rocketchip.{L2Crossbar,L2CrossbarModule,L2CrossbarBundle}
+import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
 import uncore.tilelink2.TLWidthWidget
 
-trait PeripheryXilinxVC707PCIeX1 extends L2Crossbar {
+trait PeripheryXilinxVC707PCIeX1 extends TopNetwork {
 
   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
   l2.node := xilinxvc707pcie.master
@@ -15,11 +15,11 @@ trait PeripheryXilinxVC707PCIeX1 extends L2Crossbar {
   intBus.intnode := xilinxvc707pcie.intnode
 }
 
-trait PeripheryXilinxVC707PCIeX1Bundle extends L2CrossbarBundle {
+trait PeripheryXilinxVC707PCIeX1Bundle extends TopNetworkBundle {
   val xilinxvc707pcie = new XilinxVC707PCIeX1IO
 }
 
-trait PeripheryXilinxVC707PCIeX1Module extends L2CrossbarModule {
+trait PeripheryXilinxVC707PCIeX1Module extends TopNetworkModule {
   val outer: PeripheryXilinxVC707PCIeX1
   val io: PeripheryXilinxVC707PCIeX1Bundle
 

diff --git a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
index a7cf844c10116211fccf5b1347650a5a5a1d09d7..fabfe304506cbac3999605b3d668773dfadcb4e4 100644 (file)
--- a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
+++ b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
@@ -167,27 +167,27 @@ class vc707axi_to_pcie_x1() extends BlackBox
 
 class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
 {
-  val slave = AXI4SlaveNode(AXI4SlavePortParameters(
+  val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
       address       = List(AddressSet(0x60000000L, 0x1fffffffL)),
       executable    = true,
       supportsWrite = TransferSizes(1, 256),
       supportsRead  = TransferSizes(1, 256),
       interleavedId = Some(0))), // the Xilinx IP is friendly
-    beatBytes = 8))
+    beatBytes = 8)))
 
-  val control = AXI4SlaveNode(AXI4SlavePortParameters(
+  val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
       address       = List(AddressSet(0x50000000L, 0x03ffffffL)),
       supportsWrite = TransferSizes(1, 4),
       supportsRead  = TransferSizes(1, 4),
       interleavedId = Some(0))), // no read interleaving b/c AXI-lite
-    beatBytes = 4))
+    beatBytes = 4)))
 
-  val master = AXI4MasterNode(AXI4MasterPortParameters(
+  val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(
     masters = Seq(AXI4MasterParameters(
       id      = IdRange(0, 1),
-      aligned = false))))
+      aligned = false)))))
 
   lazy val module = new LazyModuleImp(this) {
     // The master on the control port must be AXI-lite