src/soc/bus/test/wb_rw.py

   1 """Wishbone read/write utility routines
   2 """
   3
   4
   5 def wb_write(bus, addr, data, sel=True):
   6
   7     # write wb
   8     yield bus.we.eq(1)
   9     yield bus.cyc.eq(1)
  10     yield bus.stb.eq(1)
  11     yield bus.sel.eq(0b1111 if sel else 0b1) # 32-bit / 8-bit
  12     yield bus.adr.eq(addr)
  13     yield bus.dat_w.eq(data)
  14
  15     # wait for ack to go high
  16     while True:
  17         ack = yield bus.ack
  18         print ("ack", ack)
  19         if ack:
  20             break
  21         yield # loop until ack
  22         yield bus.stb.eq(0) # drop stb so only 1 thing into pipeline
  23
  24     # leave cyc/stb valid for 1 cycle while writing
  25     yield
  26
  27     # clear out before returning data
  28     yield bus.cyc.eq(0)
  29     yield bus.stb.eq(0)
  30     yield bus.we.eq(0)
  31     yield bus.adr.eq(0)
  32     yield bus.sel.eq(0)
  33     yield bus.dat_w.eq(0)
  34
  35
  36 def wb_read(bus, addr, sel=True):
  37
  38     # read wb
  39     yield bus.cyc.eq(1)
  40     yield bus.stb.eq(1)
  41     yield bus.we.eq(0)
  42     yield bus.sel.eq(0b1111 if sel else 0b1) # 32-bit / 8-bit
  43     yield bus.adr.eq(addr)
  44
  45     # wait for ack to go high
  46     while True:
  47         ack = yield bus.ack
  48         print ("ack", ack)
  49         if ack:
  50             break
  51         yield # loop until ack
  52         yield bus.stb.eq(0) # drop stb so only 1 thing into pipeline
  53
  54     # get data on same cycle that ack raises
  55     data = yield bus.dat_r
  56
  57     # leave cyc/stb valid for 1 cycle while reading
  58     yield
  59
  60     # clear out before returning data
  61     yield bus.cyc.eq(0)
  62     yield bus.stb.eq(0)
  63     yield bus.we.eq(0)
  64     yield bus.adr.eq(0)
  65     yield bus.sel.eq(0)
  66     return data
  67