src/soc/fu/alu/pipe_data.py

   1 from soc.fu.alu.alu_input_record import CompALUOpSubset
   2 from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
   3
   4
   5 class ALUInputData(FUBaseData):
   6     regspec = [('INT', 'ra', '0:63'),  # RA
   7                ('INT', 'rb', '0:63'),  # RB/immediate
   8                ('XER', 'xer_so', '32'),  # XER bit 32: SO
   9                ('XER', 'xer_ca', '34,45')]  # XER bit 34/45: CA/CA32
  10
  11     def __init__(self, pspec):
  12         super().__init__(pspec, False)
  13         # convenience
  14         self.a, self.b = self.ra, self.rb
  15
  16
  17 class ALUOutputData(FUBaseData):
  18     regspec = [('INT', 'o', '0:63'),
  19                ('CR', 'cr_a', '0:3'),
  20                ('XER', 'xer_ca', '34,45'),  # bit0: ca, bit1: ca32
  21                ('XER', 'xer_ov', '33,44'),  # bit0: ov, bit1: ov32
  22                ('XER', 'xer_so', '32')]
  23
  24     def __init__(self, pspec):
  25         super().__init__(pspec, True)
  26         # convenience
  27         self.cr0 = self.cr_a
  28
  29
  30 class ALUPipeSpec(CommonPipeSpec):
  31     regspec = (ALUInputData.regspec, ALUOutputData.regspec)
  32     opsubsetkls = CompALUOpSubset