src/soc/fu/alu/test/test_pipe_caller.py

   1 import random
   2 from soc.fu.alu.pipe_data import ALUPipeSpec
   3 from soc.fu.alu.pipeline import ALUBasePipe
   4 from openpower.test.common import (TestAccumulatorBase, ALUHelpers)
   5 from openpower.endian import bigendian
   6 from openpower.decoder.isa.all import ISA
   7 from openpower.decoder.power_enums import (XER_bits, Function)
   8 from openpower.decoder.power_decoder2 import (PowerDecode2)
   9 from openpower.decoder.power_decoder import (create_pdecode)
  10 from openpower.decoder.isa.caller import special_sprs
  11 import unittest
  12 from nmigen.cli import rtlil
  13 from nmutil.formaltest import FHDLTestCase
  14 from nmigen import Module, Signal
  15
  16 from openpower.test.alu.alu_cases import ALUTestCase
  17
  18 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  19 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  20 from nmutil.sim_tmp_alternative import Simulator, Settle
  21
  22
  23 def get_cu_inputs(dec2, sim):
  24     """naming (res) must conform to ALUFunctionUnit input regspec
  25     """
  26     res = {}
  27
  28     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2)  # RA
  29     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2)  # RB
  30     yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2)  # XER.ca
  31     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2)  # XER.so
  32
  33     print("alu get_cu_inputs", res)
  34
  35     return res
  36
  37
  38 def set_alu_inputs(alu, dec2, sim):
  39     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
  40     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
  41     # and place it into i_data.b
  42
  43     inp = yield from get_cu_inputs(dec2, sim)
  44     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
  45     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
  46
  47     yield from ALUHelpers.set_xer_ca(alu, dec2, inp)
  48     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
  49
  50
  51 class ALUIAllCases(ALUTestCase):
  52
  53     def case_ilang(self):
  54         pspec = ALUPipeSpec(id_wid=2, parent_pspec=None)
  55         alu = ALUBasePipe(pspec)
  56         vl = rtlil.convert(alu, ports=alu.ports())
  57         with open("alu_pipeline.il", "w") as f:
  58             f.write(vl)
  59
  60
  61 class TestRunner(unittest.TestCase):
  62
  63     def execute(self, alu, instruction, pdecode2, test):
  64         program = test.program
  65         sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
  66                   test.mem, test.msr,
  67                   bigendian=bigendian)
  68         gen = program.generate_instructions()
  69         instructions = list(zip(gen, program.assembly.splitlines()))
  70
  71         index = sim.pc.CIA.value//4
  72         while index < len(instructions):
  73             ins, code = instructions[index]
  74
  75             print("instruction: 0x{:X}".format(ins & 0xffffffff))
  76             print(code)
  77             if 'XER' in sim.spr:
  78                 so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
  79                 ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
  80                 ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
  81                 print("before: so/ov/32", so, ov, ov32)
  82
  83             # ask the decoder to decode this binary data (endian'd)
  84             # little / big?
  85             yield pdecode2.dec.bigendian.eq(bigendian)
  86             yield instruction.eq(ins)          # raw binary instr.
  87             yield Settle()
  88             fn_unit = yield pdecode2.e.do.fn_unit
  89             asmcode = yield pdecode2.e.asmcode
  90             dec_asmcode = yield pdecode2.dec.op.asmcode
  91             print("asmcode", asmcode, dec_asmcode)
  92             self.assertEqual(fn_unit, Function.ALU.value)
  93             yield from set_alu_inputs(alu, pdecode2, sim)
  94
  95             # set valid for one cycle, propagate through pipeline...
  96             yield alu.p.i_valid.eq(1)
  97             yield
  98             yield alu.p.i_valid.eq(0)
  99
 100             opname = code.split(' ')[0]
 101             yield from sim.call(opname)
 102             index = sim.pc.CIA.value//4
 103
 104             vld = yield alu.n.o_valid
 105             while not vld:
 106                 yield
 107                 vld = yield alu.n.o_valid
 108             yield
 109
 110             yield from self.check_alu_outputs(alu, pdecode2, sim, code)
 111             yield Settle()
 112
 113     def test_it(self):
 114         test_data = ALUTestCase().test_data
 115         m = Module()
 116         comb = m.d.comb
 117         instruction = Signal(32)
 118
 119         fn_name = "ALU"
 120         opkls = ALUPipeSpec.opsubsetkls
 121
 122         pdecode = create_pdecode()
 123         m.submodules.pdecode2 = pdecode2 = PowerDecode2(
 124             pdecode, opkls, fn_name)
 125         pdecode = pdecode2.dec
 126
 127         pspec = ALUPipeSpec(id_wid=2, parent_pspec=None)
 128         m.submodules.alu = alu = ALUBasePipe(pspec)
 129
 130         comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)
 131         comb += alu.n.i_ready.eq(1)
 132         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 133         sim = Simulator(m)
 134
 135         sim.add_clock(1e-6)
 136
 137         def process():
 138             for test in test_data:
 139                 print(test.name)
 140                 program = test.program
 141                 with self.subTest(test.name):
 142                     yield from self.execute(alu, instruction, pdecode2, test)
 143
 144         sim.add_sync_process(process)
 145         with sim.write_vcd("alu_simulator.vcd"):
 146             sim.run()
 147
 148     def check_alu_outputs(self, alu, dec2, sim, code):
 149
 150         rc = yield dec2.e.do.rc.rc
 151         cridx_ok = yield dec2.e.write_cr.ok
 152         cridx = yield dec2.e.write_cr.data
 153
 154         print("check extra output", repr(code), cridx_ok, cridx)
 155         if rc:
 156             self.assertEqual(cridx, 0, code)
 157
 158         oe = yield dec2.e.do.oe.oe
 159         oe_ok = yield dec2.e.do.oe.ok
 160         if not oe or not oe_ok:
 161             # if OE not enabled, XER SO and OV must correspondingly be false
 162             so_ok = yield alu.n.o_data.xer_so.ok
 163             ov_ok = yield alu.n.o_data.xer_ov.ok
 164             self.assertEqual(so_ok, False, code)
 165             self.assertEqual(ov_ok, False, code)
 166
 167         sim_o = {}
 168         res = {}
 169
 170         yield from ALUHelpers.get_cr_a(res, alu, dec2)
 171         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
 172         yield from ALUHelpers.get_xer_ca(res, alu, dec2)
 173         yield from ALUHelpers.get_int_o(res, alu, dec2)
 174         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 175
 176         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
 177         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
 178         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
 179         yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
 180         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 181
 182         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
 183         ALUHelpers.check_xer_ov(self, res, sim_o, code)
 184         ALUHelpers.check_xer_ca(self, res, sim_o, code)
 185         ALUHelpers.check_int_o(self, res, sim_o, code)
 186         ALUHelpers.check_xer_so(self, res, sim_o, code)
 187
 188
 189 if __name__ == "__main__":
 190     unittest.main()