a16bd78acab1c6c65702368ddd28b5a2f07f1dc1
1 from nmutil
.singlepipe
import ControlBase
2 from nmutil
.pipemodbase
import PipeModBaseChain
3 from soc
.fu
.logical
.input_stage
import LogicalInputStage
4 from soc
.fu
.logical
.main_stage
import LogicalMainStage
5 from soc
.fu
.logical
.output_stage
import LogicalOutputStage
8 class LogicalStages1(PipeModBaseChain
):
10 inp
= LogicalInputStage(self
.pspec
)
11 main
= LogicalMainStage(self
.pspec
)
15 class LogicalStages2(PipeModBaseChain
):
17 out
= LogicalOutputStage(self
.pspec
)
21 class LogicalBasePipe(ControlBase
):
22 def __init__(self
, pspec
):
23 ControlBase
.__init
__(self
)
25 self
.pipe1
= LogicalStages1(pspec
)
26 self
.pipe2
= LogicalStages2(pspec
)
27 self
._eqs
= self
.connect([self
.pipe1
, self
.pipe2
])
29 def elaborate(self
, platform
):
30 m
= ControlBase
.elaborate(self
, platform
)
31 m
.submodules
.logical_pipe1
= self
.pipe1
32 m
.submodules
.logical_pipe2
= self
.pipe2